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Freescale Semiconductor Data Sheet: Advance Information
Document Number: IMX25AEC Rev. 1, 10/2009
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
MCIMX25
i.MX25 Applications Processor for Automotive Products
Silicon Version 1.1
Package Information Plastic package Case 5284 17 x 17 mm, 0.8 mm Pitch
Ordering Information See Table 1 on page 3 for ordering information.
1
1
Introduction
2 3
The i.MX25 family of processors offers integration that tailors itself to the connectivity requirements of today's automobile infotainment systems. These processors have been architected to meet auto infotainment requirements like CAN, USB connectivity, and audio connectivity, without many of the extra features only needed for high-end applications. As a result, the i.MX25 enables many of the features only available in high-end systems, but at a price point suitable for all vehicles. At the core of the i.MX25 is Freescale's fast, proven, power-efficient implementation of the ARM926EJ-S core, with speeds of up to 400 MHz. The i.MX25 includes support for up to 133-MHz DDR2 memory, integrated 10/100 Ethernet MAC, and two on-chip USB PHYs. The automotive versions of the i.MX25 offer AEC-Q100 grade 3 qualification to meet stringent automotive quality
4
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Special Signal Considerations . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 i.MX25 Chip-Level Conditions . . . . . . . . . . . . . . . . 10 3.2 Supply Power-Up/Power-Down Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . 16 3.4 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . 22 3.6 Module Timing and Electrical Parameters . . . . . . . 40 Package Information and Contact Assignment . . . . . . . 121 4.1 400 MAPBGA--Case 17x17 mm, 0.8 mm Pitch . 121 4.2 Ground, Power, Sense, and Reference Contact Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3 Signal Contact Assignments--17x17mm, 0.8mm Pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4 i.MX25 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 127 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
(c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Features of the i.MX25 processor include the following: * Advanced power management--The heart of the device is a level of power management throughout the IC that enables the multimedia features and peripherals to achieve minimum system power consumption in active and various low-power modes. Power management techniques allow the designer to deliver a feature-rich product that requires levels of power far lower than typical industry expectations. * Multimedia powerhouse--The multimedia performance of the i.MX25 processor is boosted by a 16 KB L1 instruction and data cache system and further enhanced by an LCD controller (with alpha blending), a CMOS image sensor interface, an A/D controller (integrated touchscreen controller), and a programmable smart DMA (SDMA) controller. * 128 Kbytes on-chip SRAM--The additional 128 Kbyte on-chip SRAM makes the device ideal for eliminating external RAM in applications with small footprint RTOS. The on-chip SRAM allows the designer to enable an ultra low power LCD refresh. * Interface flexibility--The device interface supports connection to all common types of external memories: MobileDDR, DDR, DDR2, NOR Flash, PSRAM, SDRAM and SRAM, NAND Flash, and managed NAND/moviNANDTM (via the enhanced secured digital host controller (eSDHC)). Designers seeking to provide products that deliver a rich multimedia experience will find a full suite of on-chip peripherals: LCD controller and CMOS sensor interface, A/D controller (integrated touchscreen controller), parallel ATA, USB 2.0 high-speed on-the-go and full-speed host PHYs, multiple expansion card ports (high-speed MMC/SDIO host and others), fast Ethernet controller, and a variety of other common interfaces including UART, CSPI, I2C, FlexCAN, and SIM card. * Increased security--Because the need for advanced security for tethered and untethered devices continues to increase, the i.MX25 processor delivers hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, robust tamper detection, secure boot, and secure software downloads. * On-chip PHY--The device includes an HS USB OTG PHY and FS USB HOST PHY. * Fast Ethernet--For rapid external communication, a fast Ethernet controller (FEC) is included.
i.MX25 Applications Processor for Automotive Products, Rev. 1 2 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
requirements. The device is suitable for a wide range of applications, including the following: * USB connectivity * Audio streaming * Portable media player connectivity and playback with MP3, AAC, and WMA software support * External bluetooth control * Basic voice command & control * Secure black box * Smart toll collection
1.1
Ordering Information
Table 1. Ordering Information1
Part Number Silicon Version 1.1 1.1 1.1 1.1 Projected Temperature Range (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 Package 17 x 17 mm, 0.8 mm pitch, MAPBGA-400 17 x 17 mm, 0.8 mm pitch, MAPBGA-400 17 x 17 mm, 0.8 mm pitch, MAPBGA-400 17 x 17 mm, 0.8 mm pitch, MAPBGA-400
MCIMX251AVM4! MCIMX251AJM4 MCIMX255AVM4! MCIMX255AJM4
1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: Indicated by the Icon (!)
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 1 provides ordering information for the i.MX25.
1.2
Block Diagram
NOR Flash/ PSRAM
DDR2 / MDDR
NAND Flash
Ext. Graphics Accelerator
Camera Sensor
LCD Display 1
ARM(R) Processor Domain (AP)
External Memory Interface (EMI) CSI LCDC / SLCDC
Smart DMA
ARM9 Platform ARM926EJ-S L1 I/D cache
ARM Peripherals
SSI AUDMUX I2 C(3) HS USBOTG
HS USB OT GPHY
Shared Domain
SPBA
HS USB Host
FS USB Host PHY
SDMA Peripherals
AVIC MAX AIPS (2) ETM
UART(2) CSPI eSDHC(2) FlexCAN(2) ECT IOMUX IIM RTICv3 RNGB SCC DRYICE KPP PWM(4) Timers RTC WDOG GPT(4) GPIO(3) EPIT(2)
SSI(1) ESAI UART(3) CSPI(2) ADC/TSC SIM(2) ATA FEC
Internal Memory
Fusebox
1-WIRE
Audio/Power Management
JTAG
Bluetooth
MMC/SDIO or WLAN
Keypad
Access. Conn.
Figure 1. i.MX25 Simplified Interface Block Diagram
i.MX25 Applications Processor for Automotive Products, Rev. 1 4 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Figure 1 shows the simplified interface block diagram.
2
Features
Table 2. i.MX25 Digital and Analog Modules
Block Mnemonic 1-WIRE ARM9 or ARM926 Block Name 1-Wire Interface ARM926 platform and memory ATA module Subsystem Connectivity peripherals ARM(R) Brief Description 1-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example: Dallas DS2502. The ARM926 Platform consists of the ARM926EJ-STM core, the ETM real-time debug modules, a 5x5 Multi-Layer AHB crossbar switch, and a "primary AHB" complex. It contains the 16-Kbyte L1 instruction cache, 16-Kbyte L1 data cache, 32-Kbyte ROM and 128-Kbyte RAM. The ATA module is an AT attachment host interface. Its main use is to interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA device over a number of ATA signals. The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (SSIs) and peripheral serial interfaces (audio codecs). The AUDMUX has two sets of interfaces: internal ports to on-chip peripherals, and external ports to off-chip audio devices. Data is routed by configuring the appropriate internal and external ports. This block generates all clocks for the iMX25 system. The CCM also manages the ARM926 Platform's low-power modes (wait, stop, and doze) by disabling peripheral clocks appropriately for power conservation. This module is a serial interface equipped with data FIFOs. Each master/slave-configurable SPI module is capable of interfacing to both serial port interface master and slave devices. The CSPI ready (SPI_RDY) and slave select (SS) control signals enable fast data communication with fewer software interrupts. DryIce provides volatile key storage for point-of-sale (POS) terminals, and a trusted time source for digital rights management (DRM) schemes. Several tamper-detect circuits are also provided to support key erasure and time invalidation in the event of tampering. Alarms and/or interrupts can also assert if tampering is detected. DryIce also includes a real time clock (RTC) that can be used in secure and non-secure applications. The external memory interface (EMI) module provides access to external memory for the ARM and other masters. It is composed of four main submodules: * M3IF provides arbitration between multiple masters requesting access to the external memory. * Enhanced SDRAM/LPDDR memory controller (ESDCTL) interfaces to DDR2 and SDR interfaces. * NAND Flash controller (NFC) provides an interface to NAND Flash memories. * Wireless external interface memory controller (WEIM) interfaces to NOR Flash and PSRAM.
ATA
Connectivity peripherals Multimedia peripherals
AUDMUX
Digital audio mux
CCM
Clock control module Configurable serial peripheral interface
Clocks
CSPI(3)
Connectivity peripherals
DRYICE
DryIce module Security
EMI
External memory interface
Connectivity peripherals
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 2 describes the digital and analog modules of the device.
Table 2. i.MX25 Digital and Analog Modules (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Block Mnemonic EPIT(2) Block Name Subsystem Brief Description Each enhanced periodic interrupt timer (EPIT) is a 32-bit set-and-forget timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler to adjust the input clock frequency to the required time setting for the interrupts, and the counter value can be programmed on the fly. ESAI provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other DSPs. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. The features of the eSDHC module, when serving as host, include the following: * Conforms to the SD host controller standard specification version 2.0 * Compatible with the JEDEC MMC system specification version 4.2 * Compatible with the SD memory card specification version 2.0 * Compatible with the SDIO specification version 1.2 * Designed to work with SD memory, miniSD memory, SDIO, miniSDIO, SD combo, MMC and MMC RS cards * Configurable to work in one of the following modes: --SD/SDIO 1-bit, 4-bit --MMC 1-bit, 4-bit, 8-bit * Full-/high-speed mode * Host clock frequency variable between 32 kHz and 52 MHz * Up to 200-Mbps data transfer for SD/SDIO cards using four parallel data lines * Up to 416-Mbps data transfer for MMC cards using eight parallel data lines The Ethernet media access controller (MAC) is designed to support both 10and 100-Mbps Ethernet networks compliant with IEEE 802.3(R) standard. An external transceiver interface and transceiver function are required to complete the interface to the media The controller area network (CAN) protocol is primarily designed to be used as a vehicle serial data bus running at 1 MBps.
Timer Enhanced peripherals periodic interrupt timer
ESAI
Enhanced serial audio interface
Connectivity peripherals
eSDHC(2)
Connectivity Enhanced peripherals multimedia card/ secure digital host controller
FEC
Fast ethernet controller
Connectivity peripherals
FlexCAN(2)
Controller area network module General purpose I/O modules General purpose timers
Connectivity peripherals
GPIO(4)
System control Used for general purpose input/output to external ICs. Each GPIO module peripherals supports 32 bits of I/O. Timer peripherals Each GPT is a 32-bit free-running or set-and-forget mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in set-and-forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock.
GPT(4)
i.MX25 Applications Processor for Automotive Products, Rev. 1 6 Freescale Semiconductor
Table 2. i.MX25 Digital and Analog Modules (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Block Mnemonic I2C(3) Block Name I2C module Subsystem Connectivity peripherals Brief Description Inter-IC Communication (I2C) is an industry-standard, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. I2C is suitable for applications requiring occasional communications over a short distance between many devices. The interface operates up to 100 kbps with maximum bus loading and timing. The I2C system is a true multiple-master bus, including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring a fixed value. Each I/O multiplexer provides a flexible, scalable multiplexing solution: * Up to eight output sources multiplexed per pin * Up to four destinations for each input pin * Unselected input paths are held at constant level for reduced power consumption KPP can be used for either keypad matrix scanning or general purpose I/O. LCDC provides display data for external gray-scale or color LCD panels. LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive color or CSTN), and active-matrix color (active color or TFT) LCD panels. MAX concurrently supports up to five simultaneous connections between master ports and slave ports. MAX allows for concurrent transactions to occur from any master port to any slave port. The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4x16 data FIFO to generate sound.
IIM
IC Identification Module
Security
IOMUX
I/O multiplexer Pins
KPP LCDC
Keypad port LCD Controller
Connectivity peripherals Multimedia peripherals
MAX
ARM platform ARM platform multilayer AHB crossbar switch Pulse width modulation Connectivity peripherals
PWM(4)
SDMA SIM(2)
Smart DMA engine Subscriber identity module interface Secure JTAG interface Smart LCD controller
System control The SDMA provides DMA capabilities inside the processor. It is a shared module that implements 32 DMA channels. Connectivity peripherals The SIMv2 is an asynchronous interface with additional features for allowing communication with smart cards conforming to the ISO/IEC 7816 specification. The SIM is designed to facilitate communication to SIM cards or pre-paid phone cards.
SJC SLCD SPBA
System control The system JTAG controller (SJC) provides debug and test control with peripherals maximum security. Multimedia peripherals The SLCDC module transfers data from the display memory buffer to the external display device.
System control The SPBA controls access to the shared peripherals. It supports shared Shared peripheral ownership and access rights to an owned peripheral. peripheral bus arbiter
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 7
Table 2. i.MX25 Digital and Analog Modules (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Block Mnemonic SSI(2) Block Name Subsystem Brief Description The SSI is a full-duplex serial port that allows the processor to communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the inter-IC sound bus standard (I2S). The SSIs interface to the AUDMUX for flexible audio routing. The touchscreen controller and associated analog-to-digital converter (ADC) together provide a resistive touchscreen solution. The module implements simultaneous touchscreen control and auxiliary ADC operation for temperature, voltage, and other measurement functions. Each of the UART modules supports the following serial data transmit/receive protocols and configurations: * 7- or 8-bit data words, one or two stop bits, programmable parity (even, odd, or none) * Programmable baud rates up to 4 MHz. This is a higher maximum baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard and previous Freescale UART modules. 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud * IrDA-1.0 support (up to SIR speed of 115200 bps) * Option to operate as 8-pins full UART, DCE, or DTE The USB module provides high-performance USB On-The-Go (OTG) and host functionality (up to 480 Mbps), compliant with the USB 2.0 specification, the OTG supplement, and the ULPI 1.0 Low Pin Count specification. The module has DMA capabilities for handling data transfer between internal buffers and system memory. An OTG HS PHY and HOST FS PHY are also integrated.
I2S/SSI/AC97 Connectivity interface peripherals
TSC (and ADC) Touchscreen Multimedia controller (and peripherals A/D converter) UART(5) UART interface Connectivity peripherals
USBOTG USBHOST
High-speed USB on-the-go
Connectivity peripherals
2.1
Special Signal Considerations
Special signal considerations are listed in Table 3. The package contact assignment is found in Section 4, "Package Information and Contact Assignment." Signal descriptions are provided in the reference manual.
.
Table 3. Signal Considerations
Signal BAT_VDD CLK0 CLK_SEL EXT_ARMCLK DryIce backup power supply input. Clock-out pin; renders the internal clock visible to users for debugging. The clock source is controllable through CRM registers. This pin can also be configured (via muxing) to work as a normal GPIO. Used to select the ARM clock source from MPLL out or from external EXT_ARMCLK. In normal operation, CLK_SEL should be connected to GND. Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin, so it must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (via muxing) to work as a normal GPIO. Description
MESH_C, MESH_D Wire-mesh tamper detect pins that can be routed at the PCB board to detect attempted tampering of a protected wire. When security measures are implemented, MESH_C should be pulled-up to NVCC_DRYICE and triggers a tamper event when floating or when connected to MESH_D. MESH_D should be pulled-down to GND and triggers an event when floating or connected to MESH_C. These pins can be left unconnected if the DryIce security features are not being used.
i.MX25 Applications Processor for Automotive Products, Rev. 1 8 Freescale Semiconductor
Table 3. Signal Considerations (continued)
Signal NVCC_DRYICE OSC_BYP Description DryIce power supply output. Source can be SoC supply or backup supply. This pin can be used to power external components (external tamper detect, wire-mesh tamper detect). The 32 kHz oscillator bypass-control pin. If this signal is pulled down, then OSC32K_EXTAL and OSC32K_XTAL analog pins should be tied to the external 32.768 kHz crystal circuit. If on the other hand the signal is pulled up, then the external 32 kHz oscillator output clock must be connected to OSC32K_EXTAL analog pin, and OSC32K_XTAL can be no connect (NC). These analog pins are connected to an external 32 kHz CLK circuit depending on the state of OSC_BYP pin (see the description of OSC_BYP under the preceding bullet). The 32 kHz reference CLK is required for normal operation. An interrupt from PMIC, which should be connected to a low-battery detection circuit. This signal is internally connected to an on-chip 100 k pull-down device. If there is no low-battery detection, then users can tie this pin to GND via a pull-down resistor, or leave the signal as NC. This pin can also be configured to work as a normal GPIO. External ADC reference voltage. REF may be tied to GND if the user plans to only use the internally generated 2.5 V reference supply. Must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k) is allowed, but the value should be much smaller than the on-chip 100-k pull-up. DryIce external tamper detect pins, active high. If either TAMPER_A or TAMPER_B asserted, then external tampering is detected. These pins can be left unconnected if the DryIce security features are not being used. For Freescale factory use only. This signal is internally connected to an on-chip pull-down device. Users must either float this signal or tie it to GND. Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin, so it must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (via muxing) to work as a normal GPIO. Determines the reference current for the USB PHY1 bandgap reference. An external 10 k 1% resistor to GND is required. The output impedance of these signals is expected at 10 . It is recommended to also have on-board 33 series resistors (close to the pins).
OSC32K_EXTAL OSC32K_XTAL POWER_FAIL
REF SJC_MOD
TAMPER_A, TAMPER _B TEST_MODE UPLL_BYPCLK
USBPHY1_RREF USBPHY2_DM USBPHY2_DP
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 9
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
3
3.1
Electrical Characteristics
i.MX25 Chip-Level Conditions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
This section provides the device-level and module-level electrical characteristics for the i.MX25.
This section provides the chip-level electrical characteristics for the IC.
3.1.1
DC Absolute Maximum Ratings
CAUTION Stresses beyond those listed under Table 4 may cause permanent damage to the device. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 4 gives stress ratings only--functional operation of the device is not implied beyond the conditions indicated in Table 5.
Table 4. DC Absolute Maximum Ratings
Parameter Symbol QVDD VDDIOmax Vesd Human body model (HBM) Charge device model (CDM) Machine model (MM) -- -- -- VImax Tstorage -0.5 -40 2500 400 200 NVDD + 0.3 105 V
oC
Table 4 provides the DC absolute maximum operating conditions. * * *
Min. -0.5 -0.5
Max. 1.52 3.6
Units V V V
Supply voltage Supply voltage (level shift i/o) ESD damage immunity:
Input voltage range Storage temperature range
3.1.2
DC Operating Conditions
Table 5. DC Operating Conditions
Parameter Symbol QVDD QVDD VDD_BAT NVDD_GPIO1 Min. 1.15 1.38 1.15 1.75 Typ. 1.34 1.45 -- -- Max. 1.52 1.52 1.55 3.6 Units V V V V
Table 5 provides the DC recommended operating conditions.
Core supply voltage (at 266 MHz) Core supply voltage (at 400 MHz) Coin battery BAT_VDD
1
I/O supply voltage, GPIO NFC,CSI,SDIO
i.MX25 Applications Processor for Automotive Products, Rev. 1 10 Freescale Semiconductor
Table 5. DC Operating Conditions (continued)
Parameter I/O supply voltage, GPIO CRM,LCDC,JTAG,MISC I/O supply voltage DDR (Mobile DDR mode) EMI1, EMI2 I/O supply voltage DDR (DDR2 mode) EMI1,EMI2 I/O supply voltage DDR (SDRAM mode) EMI1,EMI2 Supply of USBPHY1 (HS) USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,USBPHY1_VDDA Supply of USBPHY2 (FS) USBPHY2_VDD Supply of OSC24M OSC24M_VDD Supply of PLL MPLL_VDD,UPLL_VDD Supply of touchscreen ADC NVCC_ADC External reference of touchscreen ADC Ref Fusebox program supply voltage FUSE_VDD2 Supply output3 NVCC_DRYICE Operating ambient temperature
1 2
Symbol NVDD_GPIO2 NVDD_MDDR NVDD_DDR2 NVDD_SDRAM VDD_usbphy1 VDD_usbphy2 VDD_OSC24M VDD_PLL VDD_tsc Vref FUSEVDD (program mode) VDD_ TA
Min. 3.0 1.75 1.75 1.75 3.17 3.0 3.0 1.4 3.0 2.5 -- 1.0 -40
Typ. 3.3 -- -- -- 3.3 3.3 3.3 -- 3.3
Max. 3.6 1.95 1.9 3.6 3.43 3.6 3.6 1.65 3.6
Units -- V V V V V V V V V V V
oC
VDD_tsc VDD_tsc 3.6 -- -- -- 1.55 85
VDD_BAT must always be powered by battery in security application. In non-security case, VDD_BAT can be connected to QVDD. The fusebox read supply is connected to supply of the full speed USBPHY2_VDD. FUSE_VDD is only used for programming. It is recommended that FUSE_VDD be connected to ground when not being used for programming. See Table 6 for current parameters. 3 NVCC_DRYICE is supply output. A 0.1-F external capacitor should be connected to it.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
3.1.3
Fusebox Supply Current Parameters
Table 6. Fusebox Supply Current Parameters
Parameter Symbol Iprogram Min. 26 Typ. 35 Max. 62 Units mA
eFuse program current1 Current to program one eFuse bit The associated VDD_FUSE supply = 3.6 V eFuse read current2 Current to read an 8-bit eFuse word
1 2
Iread
--
12.5
15
mA
The current Iprogram is during program time (tprogram). The current Iread is present for approximately 50 ns of the read access to the 8-bit word.
3.1.4
Interface Frequency Limits
Table 7. Interface Frequency Limits
Parameter JTAG: TCK Frequency of Operation OSC24M_XTAL Oscillator OSC32K_XTAL Oscillator Min. DC -- -- Typ. 5 24 32.768 Max. 10 -- -- Units MHz MHz KHz
Table 7 provides information for interface frequency limits.
3.1.5
USB_PHY Current Consumption
Table 8. USB PHY Current Consumption1
Parameter Conditions Rx Full speed Tx Rx High speed Suspend Tx -- Rx Full Speed Tx Rx Low Speed Tx Typ. Max. Unit (@Typ. Temp) (@Max. Temp) 11.4 22,6 21.5 33.8 0.6 120 25 252 5.5 50 -- -- -- -- 100 -- -- -- -- A A mA A mA A mA
Table 8 provides information for USB_PHY current consumption.
Analog supply USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD, USBPHY1_VDDA (3.3 V)
Analog supply USBPHY2_VDD (3.3 V)
All supplies
1
Suspend
Values must be verified
i.MX25 Applications Processor for Automotive Products, Rev. 1 12 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 6 lists the fusebox supply current parameters.
3.1.6
Power Modes
Table 9. i.MX25 Power Mode Settings
Power Mode
Core/Clock/Module Doze ARM core Well bias MCU PLL USB PLL OSC24M OSC32K Other modules
1
Wait In wait-for-interrupt mode Off On Off On On Off
Stop/Sleep1 -- On Off Off Off On Off
Run (266 MHz) Run (400 MHz) Active @ 266 MHz Off On On On On On Active @ 400 MHz Off On On On On On
Platform clock is off On On Off On On Off
Sleep mode differs from stop mode in that the core voltage is reduced to 1 V.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 13
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Table 9 describes the core, clock, and module settings for the different power modes of the processor.
Table 10 shows typical current consumption for the various power supplies under the various power modes.
Table 10. i.MX25 Power Mode Current Consumption
Power Group NVCC_EMI NVCC_CRM NVCC_ OTHER Power Supplies NVCC_EMI1 NVCC_EMI2 NVCC_CRM NVCC_SDIO NVCC_CSI NVCC_NFC NVCC_JTAG NVCC_LCDC NVCC_MISC NVCC_ADC OSC24M_ VDD MPLL_VDD UPLL_VDD QVDD USBPHY1_ VDDA USBPHY1_ VDDA_VBIAS USBPHY1_ UPLL_VDD USBPHY2_ VDD Voltage Setting 3.0 V 3.0 V 3.0 V Current Consumption for Power Modes1 Doze 5 A 1.15 A 31.2 A Wait 3.15 A 4.31 29.5 Stop 3.51 A 0.267 31.7 A Sleep 3.61 A 0.32 32.1
NVCC_ADC OSC24M PLL_VDD QVDD USBPHY1_ VDDA USBPHY1_ VDDA_VBIAS USBPHY1_ UPLL_VDD USBPHY2
1
3.0 V 3.0 V 1.4 V 1.15 V 3.17 V 3.17 V 3.17 V 3.0 V
163 A 906 A 6.83 mA 8.79 mA 240 A 0.6 201 158 A
3.25 903 6.83 m 11.28 mA 240 1.46 201 0158
1.14 10.2 mA 38.9 842 A1 241 0.328 191 164
0.871 10.5 39.1 665 A 242 0.231 191 164
Values are typical, under typical use conditions.
In the reduced power mode, shown in Table 11, the i.MX25 is powered down, while the RTC clock and the secure keys (in secure-use case), remain operational. BAT_VDD is tied to a battery while all other supplies are turned off. NOTE In this low-power mode, i.MX25 cannot be woken up with an interrupt; it must be powered back up before it can detect any events.
Table 11. iMX25 Reduced Power Mode Current Consumption
Power Group BAT_VDD Power Supply BAT_VDD Voltage Setting 1.15 V 1.55 V Typical Current Consumption 9.95 A 12.6 A
i.MX25 Applications Processor for Automotive Products, Rev. 1 14 Freescale Semiconductor
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3.2
Supply Power-Up/Power-Down Requirements and Restrictions
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Any i.MX25 board design must comply with the power-up and power-down sequence guidelines given in this section to ensure reliable operation of the device. Recommended power-up and power-down sequences are given in the following subsections. CAUTION Deviations from the guidelines in this section may result in the following situations: * * * Excessive current during power-up phase Prevention of the device from booting Irreversible damage to the i.MX25 (worst-case scenario)
NOTE For security applications, the coin battery must be connected during both power-up and power-down sequences to ensure that security keys are not unintentionally erased.
3.2.1
Power-Up Sequence
The following power-up sequence is recommended: 1. Assert power on reset (POR). 2. Turn on digital logic domain and I/O power supplies VDDn and NVCCx. 3. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD, MPPLL_VDD, UPLL_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses are not being programmed). The minimum time between turning on each power supply is the time it takes for the previous supply to be stable. 4. Negate the POR signal. * NOTE The user is advised to connect FUSEVDD to GND except when fuses are being programmed, in order to prevent unintentional blowing of fuses. Other power-up sequences may be possible; however, the above sequence has been verified and is recommended. There is a 1-ms minimum time between supplies coming up, and a 1-ms minimum time between POR_B assert and deassert.
* *
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 15
Figure 2 shows the power-up sequence diagram. After POR_B is asserted, Core VDD and NVDDx can be powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up.
POR_B
QVDD and NVDD
Analog Supplies
Figure 2. Power-Up Sequence Diagram
3.2.2
Power-Down Sequence
There are no special requirements for the power-down sequence. All power supplies can be shut down at the same time.
3.3
Thermal Characteristics
The thermal resistance characteristics for the device are given in Table 12. These values were measured under the following conditions: * Two-layer substrate * Substrate solder mask thickness: 0.025 mm * Substrate metal thicknesses: 0.016 mm * Substrate core thickness: 0.200 mm * Core via I.D: 0.118 mm, Core via plating 0.016 mm. * Flag: Trace style with ground balls under the die connected to the flag * Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K * Mold compound: Generic mold compound; k = 0.9 W/m K
Table 12. Thermal Resistance Data
Rating Junction to ambient1 natural convection Junction to ambient1 natural convection Junction to ambient1 (@200 ft/min) Condition Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) -- Symbol ReJA ReJA ReJMA ReJMA ReJB Value 55 33 46 29 22 Unit C/W C/W C/W C/W C/W
Junction to ambient1 (@200 ft/min) Junction to boards2
i.MX25 Applications Processor for Automotive Products, Rev. 1 16 Freescale Semiconductor
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Table 12. Thermal Resistance Data (continued)
Rating Junction to case (top)3 Junction to package top4
1
Condition -- Natural convection
Symbol ReJCtop JT
Value 13 2
Unit C/W C/W
Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 2 Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for this package. 3 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written as Psi-JT.
3.4
I/O DC Parameters
This section includes the DC parameters of the following I/O types: * DDR I/O: Mobile DDR (mDDR), double data rate (DDR2), or synchronous dynamic random access memory (SDRAM) * General purpose I/O (GPIO) NOTE The term `OVDD' in this section refers to the associated supply rail of an input or output. The association is shown in the "Signal Multiplexing" chapter of the reference manual.
3.4.1
DDR I/O DC Parameters
The DDR pad type is configured by the IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register (see the External Signals and Pin Multiplexing chapter of the i.MX25 Reference Manual for details).
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 17
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3.4.1.1
DDR_TYPE = 00 Standard Setting DDR I/O DC Parameters
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 13 shows the I/O parameters for mobile DDR. These settings are suitable for mDDR and DDR2 1.8V ( 5%) applications.
Table 13. Mobile DDR I/O DC Electrical Characteristics
DC Electrical Characteristics High-level output voltage Symbol Voh Test Conditions IOH = -1mA IOH = Specified Drive IOL = 1mA IOL = Specified Drive Voh = 0.8 x OVDDV Standard Drive High Drive Max. Drive Vol = 0.2 x OVDDV Standard Drive High Drive Max. Drive -- -- -- -100 VI = 0 VI = OVDD VI = OVDD or 0 VI = VDD or 0 -- -- -- Min. OVDD - 0.08 0.8 x OVDD -- Typ. -- Max. -- Units V Notes 1
Low-level output voltage
Vol
--
0.08 0.2 x OVDD --
V
High-level output current
I Ioh
-- -3.6 -7.2 -10.8 -- 3.6 7.2 10.8 0.7 x OVDD -0.3 OVDD 0 -- -- -- -- --
-- mA
Low-level output current
I Iol
-- mA OVDD+0.3 0.3 x OVDD 100 -- 110 60 990 1220 V V mV mV nA nA nA
--
High-level DC CMOS input voltage Low-level DC CMOS input voltage Differential receiver VTH+ Differential receiver VTHInput current (no pull-up/down) High-impedance I/O supply current High-impedance core supply current
VIH VIL VTH+ VTHIIN Icc-ovdd Icc-vddi
--
2, 3 2, 3
Note: 1. Simulation circuit for parameters Voh and Vol for I/O cells is below 2. Minimum condition: BCS model, 1.95 V, and -40 C. Typical condition: typical model, 1.8 V, and 25 C. Maximum condition: wcs model, 1.65 V, and 105 C. 3. Typical condition: typical model, 1.8 V, and 25 C. Maximum condition: BCS model, 1.95 V, and 105 C.
i.MX25 Applications Processor for Automotive Products, Rev. 1 18 Freescale Semiconductor
3.4.1.2
DDR_TYPE = 01 SDRAM I/O DC Parameters
Table 14. SDRAM DC Electrical Characteristics
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 14 shows the DC I/O parameters for SDRAM.
DC Electrical Characteristics High-level output voltage
Symbol Voh
Test Conditions Ioh = Specified Drive (Ioh = -4, -8, -12, -16mA) Ioh = Specified Drive (Ioh = 4, 8, 12, 16mA) Standard Drive High Drive Max. Drive Standard Drive High Drive Max. Drive -- -- VI = 0 VI = OVDD VI = OVDD or 0 VI = VDD or 0
Min. 2.4
Typ. --
Max. --
Units V
Notes 1
Low-level output voltage High-level output current
Vol I Ioh
-- -4.0 -8.0 -12.0 4.0 8.0 12.0 2.0 -0.3 V -- -- --
-- --
0.4 --
V mA
1 --
Low-level output current
I Iol
--
--
mA
--
High-level DC input voltage Low-level DC input voltage Input current (no pull-up/down)
VIH VIL IIN
-- -- -- -- --
3.6 0.8 150 80 1180 1220
V V nA nA nA
--
2, 3 2, 3
High-impedance I/O supply current Icc-ovdd High-impedance core supply current Icc-vddi
Note: 1. Simulation circuit for parameters Voh and Vol for I/O cells is below 2. Minimum condition: bcs model, OVDD = 3.6 V, and -40 C. Typical condition: typical model, OVDD = 3.3 V, and 25 C. Maximum condition: wcs model, OVDD = 3.0 V, and 105 C. 3. Typical condition: typical model, OVDD = 3.3 V, and 25 C. Maximum condition: bcs model, OVDD = 3.6 V, and 105 C.
3.4.1.3
DDR_TYPE = 10 Max Setting DDR I/O DC Parameters
Table 15. DDR2 (SSTL_18) I/O DC Electrical Characteristics
Table 15 shows the I/O parameters for DDR2 (SSTL_18).
Test Conditions -- -- -- -- -- --
DC Electrical Characteristics High-level output voltage Low-level output voltage Output min. source current Output min. sink current DC input logic high DC input logic low
Symbol Voh Vol IIoh IIol VIH(dc) VIL(dc)
Min. OVDD - 0.28 -- -13.4 13.4 OVDD/2 + 0.125 -0.3 V
Typ. -- -- -- -- -- --
Max. -- 0.28 -- -- OVDD + 0.3 OVDD/2 - 0.125
Units V V mA mA V V
Notes --
1 2 -- --
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 19
Table 15. DDR2 (SSTL_18) I/O DC Electrical Characteristics (continued)
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DC Electrical Characteristics DC input signal voltage(for differential signal) DC differential input voltage Termination voltage Input current (no pull-up/down) Symbol Vin(dc) Vid(dc) Vtt IIN Test Conditions -- -- -- VI = 0 VI = OVDD Min. -0.3 0.25 Typ. -- -- Max. OVDD + 0.3 OVDD+0.6 Units V V Notes 3 4 5 nA nA nA 9 9
OVDD/2 - 0.04 OVDD/2 OVDD/2 + 0.04 -- -- -- -- -- -- 110 60 980 1210
High-impedance I/O supply current Icc-ovdd VI = OVDD or 0 High-impedance core supply current Icc-vddi VI = VDD or 0
Note: 1. OVDD = 1.7 V; Vout = 1.42 V. (Vout-OVDD)/IOH must be less than 21 W for values of Vout between OVDD and OVDD-0.28 V. 2. OVDD = 1.7 V; Vout = 280 mV. Vout/IOL must be less than 21 W for values of Vout between 0 V and 280 mV. Simulation circuit for parameters Voh and Vol for I/O cells is below 3. Vin(dc) specifies the allowable DC excursion of each differential input 4. Vid(dc) specifies the input differential voltage required for switching. The minimum value is equal to Vih(dc) - Vil(dc). 5. Vtt is expected to track OVDD/2. 6. Minimum condition: BCS model, 1.95 V, and -40 C. Typical condition: typical model, 1.8 V, and 25 C. Maximum condition: wcs model, 1.65 V, and 105 C. 7. Typical condition: typical model, 1.8 V, and 25 C. Maximum condition: BCS model, 1.95 V, and 105 C. 8. The JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any specification in this document.
3.4.2
GPIO I/O DC Parameters
Table 16. GPIO DC Electrical Characteristics
Table 16 shows the I/O parameters for GPIO.
DC Electrical Characteristics High-level output voltage Low-level output voltage High-level output current for slow mode Symbol Voh Vol I Ioh High-level output current for fast mode I Ioh Test Conditions Ioh=-1mA Ioh = Specified Drive Iol=1mA Iol=Specified Drive Voh=0.8 x OVDD Standard Drive High Drive Max. Drive Voh=0.8 x OVDD Standard Drive High Drive Max. Drive Min. OVDD - 0.15 0.8 x OVDD -- Typ. -- -- -- -2.0 -4.0 -8.0 -- -4.0 -6.0 -8.0 -- mA -- Max. -- 0.15 0.2 x OVDD -- Units V V mA Notes 1 1 --
i.MX25 Applications Processor for Automotive Products, Rev. 1 20 Freescale Semiconductor
Table 16. GPIO DC Electrical Characteristics (continued)
DC Electrical Characteristics Low-level output current for slow mode Symbol I Iol Low-level output current for fast mode I Iol High-level DC input voltage Low-level DC input voltage Input hysteresis Schmitt trigger VT+ Schmitt trigger VT- Pull-up resistor (22 k PU) Pull-up resistor (47 k PU) Pull-up resistor (100 k PU) Pull-down resistor (100 k PD) Input current (no pull-up/down) VIH VIL VHYS VT+ VT- Rpu Rpu Rpu Rpd IIN Test Conditions Voh=0.2 x OVDD Standard Drive High Drive Max. Drive Voh=0.2 x OVDD Standard Drive High Drive Max. Drive -- -- OVDD = 3.3 V OVDD = 1.8V -- -- Vi=0 Vi=0 Vi=0 VI = OVDD VI = 0, OVDD = 3.3 V VI = OVDD = 3.3 V VI = 0, OVDD = 1.8 V VI = OVDD = 1.8 V VI = 0, OVDD = 3.3 V VI = OVDD = 3.3 V VI = 0, OVDD = 1.8 V VI = OVDD = 1.8 V Min. 2.0 4.0 8.0 -- 4.0 6.0 8.0 0.7 x OVDD -0.3 V 370 290 0.5 x OVDD -- 18.5 41 85 85 -- -- -- -- -- -- 22 47 100 100 -- OVDD 0.3 x OVDD 420 320 -- 0.5 x OVDD 25.6 55 120 120 100 60 77 50 184 0.0001 104 0.0001 V V mV V V K K K K nA 4 3 -- 2 -- -- mA -- Typ. -- Max. -- Units mA Notes --
Input current (22 k PU)
IIN
117 0.0001 64 0.0001
--
A
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 21
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Table 16. GPIO DC Electrical Characteristics (continued)
DC Electrical Characteristics Input current (47 k PU) Symbol IIN Test Conditions VI = 0, OVDD = 3.3 V VI = OVDD = 3.3 V VI = 0, OVDD = 1.8 V VI = OVDD = 1.8 V VI = 0, OVDD = 3.3 V VI = OVDD = 3.3 V VI = 0, OVDD = 1.8 V VI = OVDD = 1.8 V VI = 0, OVDD = 3.3 V VI = OVDD = 3.3 V VI = 0, OVDD = 1.8 V VI = OVDD = 1.8 V VI = 0, OVDD = 3.3 V VI = OVDD = 3.3 V VI = 0, OVDD = 1.8 V VI = OVDD = 1.8 V VI = 0, OVDD = 3.3 V VI = OVDD = 3.3 V VI = 0, OVDD = 1.8 V VI = OVDD = 1.8 V Min. 54 0.0001 30 0.0001 25 0.0001 14 0.0001 25 0.0001 14 0.0001 -- Typ. -- Max. 88 0.0001 49 0.0001 42 0.0001 23 0.0001 42 0.001 23 0.0001 688 688 560 560 490 490 410 410 Units A Notes 4
Input current (100 k PU)
IIN
--
A
Input current (100 k PD)
IIN
--
A
High-impedance I/O supply current
Icc-ovdd
--
nA
4
High-impedance core supply current Icc-vddi
--
--
nA
1. Simulation circuit for parameters Voh and Vol for I/O cells is below 2. Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. 3. Minimum condition: bcs model, OVDD = 3.6 V / 1.95 V and -40 C. Typical condition: typical model, OVDD = 3.3 V / 1.8 V, and 25 C. Maximum condition: wcs model, OVDD = 3.0 V, and 105 C. 4. Typical condition: typical model, OVDD=3.3 V / 1.8 V, and 25 C. Maximum condition: bcs model, OVDD=3.6 V / 1.95 V, and 105 C.
3.5
AC Electrical Characteristics
This section provides the AC parameters for slow and fast I/O. Figure 3 shows the load circuit for output. Figure 4 through Figure 6 show the output transition time and propagation waveforms.
From Output Under Test Test Point CL
CL includes package, probe and jig capacitance
Figure 3. Load Circuit for Output
i.MX25 Applications Processor for Automotive Products, Rev. 1 22 Freescale Semiconductor
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OVDD
Output (at pad)
20% PA1 PA1
20%
0V
Figure 4. Output Pad Transition Time Waveform
VDD 50% Input from core (1 ns transition times) tPLH 50% 0V tPHL OVDD
Output (at pad)
80% 50% 20% tTLH tTHL
80% 50% 20%
0V
Figure 5. Output Pad Propagation and Transition Time Waveform
signal "1" pdat from core VDD
signal "0" pdat from core
0
VDD 50% signal open from core tpv OVDD 50% Output (at pad)
Figure 6. Output Enable to Output Valid
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 23
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80%
80%
3.5.1
Slow I/O AC Parameters
Table 17. Slow I/O AC Parameters
Parameter Symbol Test Voltage Fduty tpr -- 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V Test Capacitance -- 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 40 0.95/0.84 1.58/1.37 2.70/2.50 3.40/3.20 1.60/1.39 2.94/2.51 1.85/1.48 2.93/2.37 3.07/2.62 5.82/4.95 3.04/2.47 5.37/4.40 1.92/2.1 2.44/2.53 2.05/2.27 2.71/2.84 2.35/2.49 3.31/3.43 2.58/2.69 3.62/3.60 3.39/3.51 5.28/5.35 3.71/3.68 5.52/5.32 1.942/2.04 2.378/2.48 2.03/2.28 2.59/2.73 2.29/2.44 3.05/3.20 2.45/2.62 3.36/3.39 3.12/3.26 4.60/4.73 3.43/3.46 4.89/4.79 Typ. Rise/Fall -- 1.36/1.11 2.19/1.77 1.80/1.40 2.80/2.14 2.23/1.79 4.05/3.17 2.90/2.17 4.56/3.40 4.22/3.30 7.94/6.19 4.73/3.50 7.70/8.10 2.96/2.96 3.7/3.64 3.32/3.67 4.39/4.51 3.58/3.61 4.9/4.786 4.17/4.27 5.86/5.61 5.03/4.89 7.6/7.14 6.03/5.75 8.80/7.96 2.923/2.95 3.541/3.53 3.19/3.59 4.10/4.33 3.42/3.49 4.46/4.45 3.86/4.07 5.34/5.22 4.58/4.53 6.61/6.32 5.48/5.34 7.75/7.16 Max. Rise/Fall 60 2.06/1.60 3.20/2.47 3.01/2.37 4.63/3.38 3.26/2.50 5.72/4.27 4.75/3.43 7.33/5.26 6.03/4.48 11.28/8.28 3.01/2.36 4.63/3.38 4.47/4.38 5.54/5.31 5.27/5.85 7.00/7.15 5.35/5.24 7.19/6.8 6.64/6.74 9.34/8.76 7.39/6.95 10.97/9.45 9.64/8.97 13.9/11.3 4.33/4.3 5.29/5.09 4.97/5.64 6.43/6.77 5.05/5.02 6.53/6.3 6.02/6.35 8.40/8.08 6.69/6.42 9.5/8.32 8.65/8.26 12.2/9.97 ns 1 ns 1 Units Notes % ns -- 1
Duty cycle Output pad transition times (max. drive)
Output pad transition times (high drive)
tpr
Output pad transition times (standard drive)
tpr
Output pad propagation delay (max. drive), 50%-50% Output pad propagation delay (high drive), 50%-50% Output pad propagation delay (standard drive), 50%-50% Output pad propagation delay (max. drive), 40%-60% Output pad propagation delay (high drive), 40%-60% Output pad propagation delay (standard drive), 40%-60%
tpo
tpo
tpo
tpo
tpo
tpo
i.MX25 Applications Processor for Automotive Products, Rev. 1 24 Freescale Semiconductor
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Table 17 shows the slow I/O AC parameters.
Table 17. Slow I/O AC Parameters (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output enable to output valid delay (max. drive), 50%-50% Output enable to output valid delay (high drive), 50%-50% Output enable to output valid delay (standard drive), 50%-50% Output enable to output valid delay (max. drive), 40%-60% Output enable to output valid delay (high drive), 40%-60% Output enable to output valid delay (standard drive), 40%-60% Output pad slew rate (max. drive) Symbol Test Voltage tpv 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V Test Capacitance 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 2.13/2.01 2.65/2.46 2.31/2.45 2.95/3.01 2.56/2.43 3.55/3.21 2.85/2.90 3.87/3.78 3.60/3.28 5.50/4.81 4.04/3.94 5.85/5.56 2.152/1.7 2.6/2.07 2.28/2.46 2.83/2.93 2.497/2.036 3.254/2.647 2.71/2.81 3.59/3.56 3.326/2.7 4.81/3.85 3.73/3.69 5.16/4.99 0.79/1.12 0.49/0.73 0.30/0.42 0.20/0.29 0.48/0.72 0.27/0.42 0.19/0.28 0.12/0.18 0.25/0.40 0.14/0.21 0.12/0.18 0.07/0.11 Typ. Rise/Fall Max. Rise/Fall Units Notes ns 1
3.3/3.045 5.072/4.609 4.038/3.639 6.142/5.423 6.11/6.47 3.76/4.00 7.81/7.73 4.81/4.82 3.91/3.604 5.21/4.598 4.65/4.64 6.31/5.95 5.35/4.70 7.93/6.603 6.65/6.21 9.47/8.49 3.25/2.68 3.88/3.17 3.62/3.92 4.50/4.62 3.75/3.135 4.8/3.9 4.31/4.23 5.75/5.54 4.9/3.9 6.9/5.4 6.04/5.77 8.28/7.61 1.30/1.77 0.84/1.23 0.54/0.73 0.35/0.50 0.76/1.10 0.41/0.62 0.34/0.49 0.34/0.49 0.40/0.59 0.21/0.32 0.20/0.30 0.11/0.17 5.937/5.36 7.776/6.694 7.58/7.44 10.3/9.43 7.97/6.836 11.58/9.338 10.9/9.22 15.5/13.3 4.93/4.162 5.842/4.846 5.77/6.24 7.20/7.32 5.633/4.782 7.117/5.84 6.89/7.01 9.23/8.71 7.269/5.95 10.12/7.86 9.81/9.11 13.4/11.8 2.02/2.58 1.19/1.58 0.91/1.20 0.60/0.80 1.17/1.56 0.63/0.86 0.58/0/79 0.36/0.49 0.60/0.83 0.32/0.44 0.34/0.47 0.20/0.27
tpv
tpv
tpv
ns
1
tpv
tpv
tps
V/ns
2
Output pad slew rate (high drive)
tps
Output pad slew rate (standard drive)
tps
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 25
Table 17. Slow I/O AC Parameters (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad dI/dt (max. drive) Symbol Test Voltage tdit 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V 3.0-3.6 V 3.0-3.6 V 1.65-1.95 V 1.65-1.95 V -- Test Capacitance 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.6 pF Min. Rise/Fall 15 16 7 7 8 9 5 5 4 4 2 2 0.82/0.47 0.74/1 1.1/1.3 1.75/1.63 1.62/1.28 1.82/1.55 1.88/2.1 2.4/2.6 0.16/0.12 0.16/0.13 -- Typ. Rise/Fall 36 38 21 22 20 21 14 15 10 10 7 7 1.1/0.76 1.1/1.5 1.43/1.6 2.67/2.22 1.9/1.56 2.28/1.87 2.2/2.4 3/3.07 0.23/0.18 0.22/0.18 -- Max. Rise/Fall 76 80 56 58 45 47 38 40 22 23 18 19 1.6/1.04 1.75/2.16 2/2 2.92/3 2.38/1.82 2.95/2.54 2.7/2.75 3.77/3.71 0.33/0.29 0.33/0.29 25 ns 5 ns 4 Units Notes mA /ns 3
Output pad dI/dt (high drive)
tdit
Output pad dI/dt (standard drive)
tdit
Input pad propagation delay without hysteresis, 50%-50% Input pad propagation delay with hysteresis, 50%-50% Input pad propagation delay without hysteresis, 40%-60% Input pad propagation delay with hysteresis, 40%-60% Input pad transition times without hysteresis Input pad transition times with hysteresis Maximum input transition times
tpi
tpi tpi
-- --
1.6 pF 1.6 pF
tpi trfi trfi trm
-- --
1.6 pF 1.6 pF 1.6 pF
--
--
Note: 1. Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 3.0 V (3.0-3.6 V range) or 1.65 V (1.65-1.95 V range), and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 3.6 V (3.0-3.6 V range) or 1.95 V (1.65-1.95 V range), and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V (3.0-3.6 V range) or 1.65 V (1.65-1.95 V range), and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V (3.0-3.6 V range) or 1.95 V (1.65-1.95 V range), and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V (3.0-3.6 V range) or 1.65 V (1.65-1.95 V range), and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3.6 V or 1.95 V (1.65-1.95 V range), and -40 C. Input transition time from pad is 5 ns (20%-80%). 5. Hysteresis mode is recommended for input with transition time greater than 25 ns.
i.MX25 Applications Processor for Automotive Products, Rev. 1 26 Freescale Semiconductor
3.5.2
Fast I/O AC Parameters
Table 18. Fast I/O AC Parameters for OVDD = 1.65-1.95 V
Parameter Symbol Fduty tpr tpr tpr tpo tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv tps tps tps Test Condition -- 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 40 0.88/0.77 1.45/1.24 1.10/0.92 1.84/1.54 1.60/1.35 2.74/2.26 1.64/1.53 2.15/2.01 1.82/1.71 2.46/2.29 2.24/2.06 3.17/2.92 1.67/1.58 2.09/1.98 1.94/1.73 2.34/2.22 2.15/1.99 2.94/2.74 1.87/1.70 2.36/2.16 2.05/1.88 2.68/2.45 2.49/2.25 3.40/3.08 1.90/1.74 2.30/2.13 2.06/1.90 2.56/2.37 2.39/2.18 3.16/2.89 0.40/0.57 0.25/0.36 0.38/0.48 0.20/0.30 0.23/0.32 0.13/0.20 Typ. -- 1.36/1.10 2.20/1.80 1.65/1.33 2.80/2.20 2.47/1.95 4.20/3.20 2.68/2.41 3.47/3.08 2.98/2.66 3.96/3.49 3.63/3.15 5.09/4.41 2.63/2.38 3.30/2.97 2.89/2.61 3.69/3.30 3.39/2.99 4.65/4.07 3.06/2.71 3.83/3.37 3.67/2.98 4.32/3.78 4.06/3.50 5.50/4.73 3.00/2.69 3.65/3.24 3.28/2.33 4.04/3.59 3.80/3.18 5.03/4.37 0.72/0.97 0.43/0.61 0.59/0.81 0.34/0.50 0.40/0.55 0.23/0.34 Max. Rise/Fall 60 2.10/1.70 3.50/2.70 2.64/2.10 4.40/3.30 3.99/3.10 6.56/4.86 4.25/3.74 5.50/4.77 4.74/4.13 6.27/5.37 5.73/4.84 8.06/6.75 4.06/3.63 5.14/4.51 4.49/3.97 5.76/5.01 5.28/4.53 7.28/6.13 4.97/4.30 6.18/5.30 5.46/4.72 6.98/5.92 6.57/5.49 8.88/7.37 4.76/4.18 5.79/5.02 5.21/4.54 6.43/5.54 6.05/5.14 8.02/6.72 1.2/1.5 0.72/0.95 0.98/1.27 0.56/0.72 0.66/0.87 0.38/0.52 Units % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns V/ns V/ns V/ns 2 1 1 1 1 Notes -- 1
Duty cycle Output pad transition times (max. drive) Output pad transition times (high drive) Output pad transition times (standard drive) Output pad propagation delay (max. drive), 50%-50% Output pad propagation delay (high drive), 50%-50% Output pad propagation delay (standard drive), 50%-50% Output pad propagation delay (max. drive), 40%-60% Output pad propagation delay (high drive), 40%-60% Output pad propagation delay (standard drive), 40%-60% Output enable to output valid delay (max. drive), 50%-50% Output enable to output valid delay (high drive), 50%-50% Output enable to output valid delay (standard drive), 50%-50% Output enable to output valid delay (max. drive), 40%-60% Output enable to output valid delay (high drive), 40%-60% Output enable to output valid delay (standard drive), 40%-60% Output pad slew rate (max. drive) Output pad slew rate (high drive) Output pad slew rate (standard drive)
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 27
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 18 shows the fast I/O AC parameters for OVDD = 1.65-1.95 V.
Table 18. Fast I/O AC Parameters for OVDD = 1.65-1.95 V (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad dI/dt (max. drive) Output pad dI/dt (high drive) Output pad dI/dt (standard drive) Input pad propagation delay without hysteresis, 50%-50% Input pad propagation delay with hysteresis, 50%-50% Input pad propagation delay without hysteresis, 40%-60% Input pad propagation delay with hysteresis, 40%-60% Input pad transition times without hysteresis Input pad transition times with hysteresis Maximum input transition times Symbol tdit tdit tdit tpi tpi tpi tpi trfi trfi trm Test Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.6 pF 1.6 pF 1.6 pF 1.6 pF 1.6 pF 1.6 pF -- Min. Rise/Fall 7 7 11 12 9 10 0.74/1 1.75/1.63 1.82/1.55 2.4/2.6 0.16/0.12 0.16/0.13 -- Typ. 43 46 31 33 27 28 1.1/1.5 2.67/2.22 2.28/1.87 3/3.07 0.30/0.18 0.30/0.18 -- Max. Rise/Fall 112 118 81 85 71 74 1.75/2.16 2.92/3 2.95/2.54 3.77/3.71 0.33/0.29 0.33/0.29 25 Units mA/ns mA/ns mA/ns ns ns ns ns ns ns ns 5 4 Notes 3
Note: 1. Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.95 V, and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.95 V and -40 C. Input transition time from pad is 5 ns (20%-80%). 5. Hysteresis mode is recommended for input with transition time greater than 25 ns.
i.MX25 Applications Processor for Automotive Products, Rev. 1 28 Freescale Semiconductor
Table 19 shows the fast I/O AC parameters for OVDD = 3.0-3.6 V.
Table 19. Fast I/O AC Parameters for OVDD = 3.0-3.6 V
Parameter Duty Cycle Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Standard Drive) Output Pad Propagation Delay (Max Drive), 50%-50% Output Pad Propagation Delay (High Drive), 50%-50% Output Pad Propagation Delay (Standard Drive), 50%-50% Output Pad Propagation Delay (Max Drive), 40%-60% Output Pad Propagation Delay (High Drive), 40%-60% Output Pad Propagation Delay (Standard Drive), 40%-60% Output Enable to Output Valid Delay (Max Drive), 50%-50% Output Enable to Output Valid Delay (High Drive), 50%-50% Output Enable to Output Valid Delay (Standard Drive), 50%-50% Output Enable to Output Valid Delay (Max Drive), 40%-60% Output Enable to Output Valid Delay (High Drive), 40%-60% Output Enable to Output Valid Delay (Standard Drive), 40%-60% Output Pad Slew Rate (Max Drive) Output Pad Slew Rate (High Drive) Output Pad Slew Rate (Standard Drive) Symbol Fduty tpr tpr tpr tpo tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv tps tps tps 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Test Condition Min. Rise/Fall Typ. Max. Rise/Fall 60 1.12/2.51 1.60/2.39 1.43/1.16 2.66/2.09 2.09/1.67 3.40/3.09 1.74/1.73 2.39/2.32 1.95/1.91 2.81/2.68 2.54/2.48 3.82/3.62 1.94/2.05 2.46/2.55 2.11/2.19 2.78/2.81 2.61/2.67 3.62/3.58 1.91/1.81 2.56/2.40 2.12/2.00 2.98/2.76 2.70/2.60 4.00/3.70 2.25/2.08 2.77/2.58 2.41/2.23 3.08/2.86 2.91/2.71 3.91/3.62 1.54/2.10 0.85/1.24 1.19/1.71 0.63/0.95 0.80/1.19 0.43/0.64 1.64/1.32 2.84/2.10 2.05/1.60 3.70/2.80 3.00/2.30 5.56/4.12 2.67/2.52 3.58/3.33 2.96/2.76 4.16/3.78 3.80/3.60 5.62/5.10 2.95/3.07 3.71/3.75 3.19/3.26 4.14/4.09 3.95/3.95 5.36/5.15 2.92/2.67 3.83/3.47 3.21/2.92 4.41/3.94 4.07/3.74 5.86/5.24 3.50/3.31 4.24/3.99 3.74/3.51 4.66/4.34 4.48/4.21 5.85/5.39 2.30/3.00 1.26/1.70 1.78/2.39 0.95/1.30 1.20/1.60 0.63/0.87 Units % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns V/ns V/ns V/ns Notes
40
0.80/0.70 1.40/1.60 1.00/0.90 1.95/1.66 1.50/1.30 2.90/2.50 1.20/1.28 1.67/1.75 1.35/1.42 1.98/2.04 1.77/1.85 2.70/2.78 1.37/1.50 1.74/1.88 1.48/1.61 1.98/2.10 1.84/1.97 2.58/2.71 1.34/1.32 1.81/1.79 1.48/1.47 2.12/2.1 1.90/1.90 2.85/2.83 1.55/1.42 1.93/1.81 1.67/1.54 2.16/2.03 2.02/1.90 2.76/2.63 0.96/1.40 0.54/0.83 0.76/1.10 0.41/0.64 0.52/0.78 0.28/0.44
1
1
1
1
1
2
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 29
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 19. Fast I/O AC Parameters for OVDD = 3.0-3.6 V (continued)
Output Pad di/dt (Max Drive) Output Pad di/dt (High Drive) Output Pad di/dt (Standard Drive) Input Pad Propagation Delay without Hysteresis, 50%-50% Input Pad Propagation Delay with Hysteresis, 50%-50% Input Pad Propagation Delay without Hysteresis, 40%-60% Input Pad Propagation Delay with Hysteresis, 40%-60% Input Pad Transition Times without Hysteresis Input Pad Transition Times with Hysteresis Maximum Input Transition Times didt didt didt tpi tpi tpi tpi trfi trfi trm
25 pF 50 pF 25 pF 50 pF 1.6pF 1.6pF 1.6pF 1.6pF 1.6pF 1.6pF --
35 37 22 23
82 86 52 55
197 207 116 121 1.404/0.97
mA/ns mA/ns ns ns ns ns ns ns ns
3
0.729/0.458 0.97/0.0649
1.203/0.938 1.172/1.187 1.713/1.535 0.879/0.977 1.434/1.12 1.854/1.427
4
1.353/1.457 1.637/1.659 2.163/1.991 0.16/0.12 0.16/0.13 -- 0.23/0.18 0.22/0.18 -- 0.33/0.29 0.33/0.29 --
5
Note: 1.Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, IO 3.0 V and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, IO 3.6 V and -40 C. Input transition time from core is 1ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, IO 3.0 V and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, IO 3.6 V and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, IO 3.0 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, IO 3.6 V and -40 C. Input transition time from pad is 5ns (20%-80%). 5. Hysteresis mode is recommended for input with transition time greater than 25 ns.
3.5.3
DDR I/O AC Parameters
The DDR pad type is configured by the IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register (see Chapter 4, "External Signals and Pin Multiplexing," in the i.MX25 Multimedia Applications Processor Reference Manual).
i.MX25 Applications Processor for Automotive Products, Rev. 1 30 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
25 pF 50 pF
46 49
108 113
250 262
mA/ns
3.5.3.1
DDR_TYPE = 00 Standard Setting I/O AC Parameters and Requirements
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 20 shows AC parameters for mobile DDR I/O. These settings are suitable for mDDR and DDR2 1.8V ( 5%) applications.
Table 20. AC Parameters for Mobile DDR I/O
Parameter Duty cycle Clock frequency Output pad transition times (max. drive) Output pad transition times (high drive) Output pad transition times (standard drive) Output pad propagation delay (max. drive), 50%-50% Output pad propagation delay (high drive), 50%-50% Output pad propagation delay (standard drive), 50%-50% Output pad propagation delay (max. drive), 40%-60% Output pad propagation delay (high drive), 40%-60% Output pad propagation delay (standard drive), 40%-60% Output enable to output valid delay (max. drive), 50%-50% Output enable to output valid delay (high drive), 50%-50% Output enable to output valid delay (standard drive), 50%-50% Output enable to output valid delay (max. drive), 40%-60% Output enable to output valid delay (high drive), 40%-60% Output enable to output valid delay (standard drive), 40%-60% Symbol Fduty f tpr tpr tpr tpo tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv Load Condition -- -- 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF Min. Rise/Fall 40 -- 0.52/0.51 0.98/0.96 1.13/1.10 2.15/2.10 2.26/2.19 4.30/4.18 0.80/1.03 1.06/1.32 1.04/1.27 1.63/1.90 1.55/1.80 2.72/3.06 0.80/0.91 1.06/1.12 1.04/1.09 1.63/1.56 1.50/1.74 2.73/2.42 1.17/1.01 1.43/1.30 1.38/1.28 1.97/1.92 1.92/1.57 3.12/3.16 1.28/1.12 1.49/1.36 1.43/1.33 1.90/1.84 1.85/1.78 2.80/2.81 Typ. 50 -- 0.79/0.72 1.49/1.34 1.74/1.55 3.28/2.92 Max. Rise/Fall 60 133 1.25/1.09 2.31/1.98 2.71/2.30 5.11/4.31 Units % MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 Notes -- 1 1
3.46/3.07 5.39/4.56 6.59/5.79 10.13/8.55 1.36/1.50 1.76/1.90 1.74/1.83 2.63/2.69 2.53/2.57 4.31/4.29 1.44/1.59 1.76/1.91 1.73/1.83 2.43/2.52 2.36/2.41 3.77/3.78 1.93/1.61 2.33/2.00 2.25/1.99 3.16/2.86 3.11/2.79 4.97/4.59 2.01/1.70 2.33/2.01 2.24/1.99 2.96/2.68 2.91/2.62 4.37/4.53 2.21/2.40 2.83/2.82 2.79/2.70 4.18/3.86 4.03/3.76 6.80/6.19 2.24/2.29 2.74/2.75 2.69/2.62 3.79/3.62 3.67/3.46 5.86/5.37 3.06/2.55 3.69/3.13 3.58/3.10 5.01/4.39 4.98/4.13 7.97/6.98 3.09/2.60 3.60/3.06 3.47/3.02 4.59/4.03 4.54/3.96 6.88/6.05
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 31
Table 20. AC Parameters for Mobile DDR I/O (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad slew rate (max. drive) Output pad slew rate (high drive) Output pad slew rate (standard drive) Output pad dI/dt (max. drive) Output pad dI/dt (high drive) Output pad di/dt (standard drive) Input pad transition times Input pad propagation delay, 50%-50% Input pad propagation delay, 40%-60% Symbol tps tps tps tdit tdit tdit trfi tpi tpi Load Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.0 pF 1.0 pF 1.0 pF Min. Rise/Fall 0.80/0.92 0.43/0.50 0.37/0.43 0.19/0.23 0.18/0.22 0.10/0.12 64 69 37 39 18 20 0.07/0.08 0.77/1.00 1.59/1.82 Typ. 1.35/1.50 0.72/0.81 0.62/0.70 0.33/0.37 0.31/0.35 0.16/0.18 171 183 100 106 50 52 0.11/0.13 1.22/1.45 2.04/2.27 Max. Rise/Fall 2.23/2.27 1.66/1.68 1.03/1.05 0.75/0.77 0.51/0.53 0.38/0.39 407 432 232 246 116 123 0.16/0.20 1.89/2.21 2.69/3.01 Units V/ns V/ns V/ns mA/ns mA/ns mA/ns ns ns ns 4 3 Notes 2
Note: 1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.95 V and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.95 V and -40 C. Input transition time from pad is 5 ns (20%-80%).
Table 21 shows the AC parameters for mobile DDR pbijtov18_33_ddr_clk I/O.
Table 21. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O
Parameter Duty cycle Clock frequency Output pad transition times (max. drive) Output pad transition times (high drive) Output pad transition times (standard drive) Symbol Fduty f tpr tpr tpr Load Condition -- -- 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 40 -- 0.52/0.51 0.98/0.96 1.13/1.10 2.15/2.10 2.26/2.19 4.30/4.18 Typ. 50 -- 0.79/0.72 1.49/1.34 1.74/1.55 3.28/2.92 Max. Rise/Fall 60 133 1.25/1.09 2.31/1.98 2.71/2.30 5.11/4.31 Units % MHz ns ns ns Notes -- 1 1
3.46/3.07 5.39/4.56 6.59/5.79 10.13/8.55
i.MX25 Applications Processor for Automotive Products, Rev. 1 32 Freescale Semiconductor
Table 21. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad propagation delay (max. drive), 50%-50% input signals and crossing of output signals Output pad propagation delay (high drive), 50%-50% input signals and crossing of output signals Output pad propagation delay (standard drive), 50%-50% input signals and crossing of output signals Output pad propagation delay (max. drive), 40%-60% input signals and crossing of output signals Output pad propagation delay (high drive), 40%-60% input signals and crossing of output signals Output pad propagation delay (standard drive), 40%-60% input signals and crossing of output signals Output enable to output valid delay (max. drive), 50%-50% Output enable to output valid delay (high drive), 50%-50% Output enable to output valid delay (standard drive), 50%-50% Output enable to output valid delay (max. drive), 40%-60% Output enable to output valid delay (high drive), 40%-60% Output enable to output valid delay (standard drive), 40%-60% Output pad slew rate (max. drive) Output pad slew rate (high drive) Output pad slew rate (standard drive) Symbol tpo Load Condition 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 1.28/1.19 1.56/1.47 1.54/1.43 2.14/2.04 2.05/1.94 3.27/3.16 1.45/1.36 1.73/1.64 1.70/1.60 2.31/2.21 2.22/2.11 3.43/3.32 1.16/1.12 1.42/1.41 1.39/1.39 1.98/2.02 1.90/1.94 3.07/3.20 1.28/1.24 1.49/1.47 1.45/1.44 1.92/1.95 1.85/1.88 2.78/2.88 0.37/0.45 0.30/0.36 0.30/0.37 0.21/0.25 0.22/0.26 0.13/0.16 Typ. 1.97/1.83 2.37/2.23 2.34/2.20 3.22/3.08 3.11/2.96 4.86/4.72 2.13/2.00 2.53/2.40 2.51/2.37 3.38/3.24 3.27/3.13 5.02/4.88 1.91/1.81 2.31/2.20 2.28/2.18 3.18/3.04 3.09/2.94 4.88/4.66 2.00/1.90 2.32/2.21 2.28/2.19 2.99/2.87 Max. Rise/Fall 2.98/2.78 3.57/3.37 3.54/3.33 4.85/4.65 4.70/4.50 7.33/7.12 3.14/2.94 3.74/3.54 3.70/3.50 5.02/4.82 4.87/4.66 7.49/7.29 3.10/2.89 3.72/3.47 3.69/3.43 5.08/4.69 4.95/4.55 7.73/7.05 3.14/2.93 3.64/3.41 3.60/3.36 4.69/4.36 Units ns Notes 1
tpo
ns
tpo
ns
tpo
ns
1
tpo
ns
tpo
ns
tpv tpv tpv tpv tpv tpv tps tps tps
ns ns ns ns ns ns V/ns V/ns V/ns
1
1
2.92/2.79 4.5894.25 4.34/4.16 6.79/6.24 0.64/0.79 0.52/0.61 0.51/0.63 0.36/0.42 0.37/0.44 0.23/0.26 1.14/1.36 0.90/1.02 091/1.06 0.63/0.67 0.65/0.72 0.39/0.40
2
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 33
Table 21. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad dI/dt (max. drive) Output pad dI/dt (high drive) Output pad dI/dt (standard drive) Input pad transition times Input pad propagation delay, 50%-50% Input pad propagation delay, 40%-60% Symbol tdit tdit tdit trfi tpi tpi Load Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.0 pF 1.0 pF 1.0 pF Min. Rise/Fall 65 70 31 33 16 17 0.07/0.08 0.84/0.84 1.66/1.66 Typ. 171 183 82 87 43 46 0.11/0.13 1.40/1.34 2.22/2.16 Max. Rise/Fall 426 450 233 245 115 120 0.16/0.20 2.25/2.16 3.06/2.97 Units mA/ns mA/ns mA/ns ns ns ns 4 Notes 3
Note: 1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.95 V and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.95 V and -40 C. Input transition time from pad is 5 ns (20%-80%).
Table 22 shows the AC requirements for mobile DDR I/O.
Table 22. AC Requirements for Mobile DDR I/O
Parameter AC input logic high AC input logic low AC differential input voltage AC differential cross point voltage for input Symbol VIH(ac) VIL(ac) Vid(ac) Vix(ac) Min. 0.8 x OVDD -0.3 0.6 x OVDD 0.4 x OVDD Max. OVDD+0.3 0.2 x OVDD OVDD+0.6 OVDD+0.6 Units V V V V
3.5.3.2
DDR_TYPE = 01 SDRAM I/O AC Parameters and Requirements
Table 23. AC Parameters for SDRAM I/O
Parameter Symbol Fduty f Load Condition -- -- Min. Rise/Fall 40 -- Typ. 50 -- Max. Rise/Fall 60 125 Units % MHz Notes -- 1
Table 23 shows AC parameters for SDRAM I/O.
Duty cycle Clock frequency
i.MX25 Applications Processor for Automotive Products, Rev. 1 34 Freescale Semiconductor
Table 23. AC Parameters for SDRAM I/O (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad transition times (max. drive) Symbol tpr Load Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF Min. Rise/Fall 0.82/0.87 1.56/1.67 1.23/1.31 2.31/2.47 2.44/2.60 4.65/4.99 0.97/1.19 2.85/3.21 1.15/1.39 3.57/3.91 2.01/1.57 5.73/6.05 1.06/1.26 1.38/1.38 1.15/1.20 1.75/1.67 1.91/2.01 2.88/2.56 0.90/1.27 1.07/1.77 1.01/1.48 1.37/2.33 1.32/2.14 2.04/3.67 1.03/1.34 1.16/1.74 1.11/1.51 1.39/2.10 1.35/2.03 1.91/3.23 1.11/1.20 0.97/0.65 0.76/0.80 0.40/0.43 0.38/0.41 0.20/0.22 Typ. Max. Rise/Fall Units ns Notes 1
1.14/1.13 1.62/1.50 2.13/2.09 3.015/2.7 7 1.71/1.68 2.39/2.22 3.22/3.12 4.53/4.16 3.38/3.27 4.73/4.38 6.38/6.23 9.05/8.23 1.69/0.75 2.17/2.46 2.02/2.30 2.93/3.27 1.72/1.93 2.51/2.77 2.54/2.85 3.66/3.97 2.45/2.69 3.54/3.77 4.10/4.51 5.84/6.13 1.53/1.73 2.18/2.47 1.96/2.23 2.78/3.12 1.72/1.93 2.45/2.71 2.37/2.66 3.35/3.67 2.30/2.52 3.26/3.50 3.59/3.97 5.06/5.36 1.44/1.89 2.19/2.87 1.66/2.51 2.51/3.69 1.58/2.16 2.38/3.23 2.06/3.09 3.06/4.46 2.02/3.00 3.01/4.36 3.00/4.91 4.40/6.90 1.54/1.94 2.26/2.88 1.74/2.44 2.55/3.54 1.65/2.15 2.43/3.16 2.03/2.89 2.95/4.13 1.99/2.83 2.89/4.03 2.76/4.30 3.98/6.01 1.74/1.75 2.42/2.46 0.92/0.94 1.39/1.30 1.16/1.19 1.76/1.66 0.61/0.63 0.93/0.87 0.59/0.60 0.89/0.82 0.31/0.32 0.47/0.43
Output pad transition times (high drive) Output pad transition times (standard drive) Output pad propagation delay (max. drive), 50%-50% Output pad propagation delay (high drive), 50%-50% Output pad propagation delay (standard drive), 50%-50% Output pad propagation delay (max. drive), 40%-60% Output pad propagation delay (high drive), 40%-60% Output pad propagation delay (standard drive), 40%-60% Output enable to output valid delay (max. drive), 50%-50% Output enable to output valid delay (high drive), 50%-50% Output enable to output valid delay (standard drive), 50%-50% Output enable to output valid delay (max. drive), 40%-60% Output enable to output valid delay (high drive), 40%-60% Output enable to output valid delay (standard drive), 40%-60% Output pad slew rate (max. drive) Output pad slew rate (high drive) Output pad slew rate (standard drive)
tpr tpr tpo tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv tps tps tps
ns ns ns ns ns ns ns ns ns ns ns ns ns ns V/ns V/ns V/ns 2 -- 1 1 1
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 35
Table 23. AC Parameters for SDRAM I/O (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad dI/dt (max. drive) Output pad dI/dt (high drive) Output pad dI/dt (standard drive) Input pad transition times Input pad propagation delay, 50%-50% Input pad propagation delay, 40%-60% Symbol tdit tdit tdit trfi tpi tpi Load Condition 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.0 pF 1.0 pF -- Min. Rise/Fall 89 94 59 62 29 31 0.07/0.08 0.35/1.17 1.18/1.99 Typ. 198 209 132 139 65 69 Max. Rise/Fall 398 421 265 279 132 139 Units mA/ns mA/ns mA/ns ns ns -- 4 Notes 3
0.11/0.12 0.16/0.20 0.63/1.53 1.16/2.04 1.45/2.35 1.97/2.85
Note: 1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 3.6 V and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3.6 V and -40 C. Input transition time from pad is 5 ns (20%-80%).
Table 24 shows AC parameters for SDRAM pbijtov18_33_ddr_clk I/O.
Table 24. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O
Parameter Duty cycle Clock frequency Output pad transition times (max. drive) Symbol Fduty f tpr Load Condition -- -- 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF Min. Rise/Fall 40 -- 0.82/0.87 1.56/1.67 1.23/1.31 2.31/2.47 2.44/2.60 4.65/4.99 1.50/1.40 1.95/1.85 1.69/1.59 2.35/2.25 2.26/2.15 3.59/3.49 Typ. 50 -- Max. Rise/Fall 60 125 Units % MHz ns Notes -- 1 1
1.14/1.13 1.62/1.50 2.13/2.09 3.015/2.7 7 1.71/1.68 2.39/2.22 3.22/3.12 4.53/4.16 3.38/3.27 4.73/4.38 6.38/6.23 9.05/8.23 2.23/2.07 3.28/3.04 2.81/2.66 4.06/3.82 2.48/2.32 3.63/3.38 3.35/3.19 4.80/4.56 3.24/3.08 4.66/4.42 4.98/4.82 7.00/6.75
Output pad transition times (high drive) Output pad transition times (standard drive) Output pad propagation delay (max. drive), 50%-50% input signals and crossing of output signals Output pad propagation delay (high drive), 50%-50% input signals and crossing of output signals Output pad propagation delay (standard drive), 50%-50% input signals and crossing of output signals
tpr tpr tpo
ns ns ns 1
tpo
ns
tpo
ns
i.MX25 Applications Processor for Automotive Products, Rev. 1 36 Freescale Semiconductor
Table 24. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Parameter Output pad propagation delay (max. drive), 40%-60% input signals and crossing of output signals Output pad propagation delay (high drive), 40%-60% input signals and crossing of output signals Output pad propagation delay (standard drive), 40%-60% input signals and crossing of output signals Output enable to output valid delay (max. drive), 50%-50% Output enable to output valid delay (high drive), 50%-50% Output enable to output valid delay (standard drive), 50%-50% Output enable to output valid delay (max. drive), 40%-60% Output enable to output valid delay (high drive), 40%-60% Output enable to output valid delay (standard drive), 40%-60% Output pad slew rate (max. drive) Output pad slew rate (high drive) Output pad slew rate (standard drive) Output pad dI/dt (max. drive) Output pad dI/dt (high drive) Output pad dI/dt (standard drive) Input pad transition times Input pad propagation delay, 50%-50% Input pad propagation delay, 40%-60% Symbol tpo Load Condition 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.0 pF 1.0 pF Min. Rise/Fall 1.67/1.57 2.11/2.02 1.85/1.75 2.52/2.42 2.42/2.32 3.76/3.66 1.37/1.34 1.77/1.83 1.55/1.56 2.15/2.29 2.07/2.18 3.28/3.65 1.46/1.42 1.77/1.81 1.60/1.59 2.07/2.18 2.01/2.09 2.96/3.26 1.11/1.20 0.60/0.65 0.75/0.81 0.40/0.43 0.38/0.41 0.20/0.22 89 95 60 63 29 31 0.07/0.08 0.56/0.69 1.38/1.51 Typ. Max. Rise/Fall Units ns Notes 1
2.39/2.24 3.45/3.21 2.97/2.82 4.23/3.99 2.65/2.49 3.79/3.55 3.51/3.36 4.97/4.72 3.40/3.25 4.83/4.59 5.15/4.99 7.17/6.92 2.22/2.02 3.53/3.12 2.77/2.63 4.30/3.92 2.46/2.30 3.87/3.47 3.28/3.21 5.02/4.67 3.20/3.08 4.92/4.50 4.84/4.90 7.21/6.89 2.28/2.07 3.54/3.13 2.71/2.56 4.15/3.78 2.47/2.30 3.82/3.41 3.12/3.02 4.72/4.37 3.05/2.91 4.64/4.23 4.34/4.37 6.45/6.13 1.74/1.75 2.63/2.48 0.93/0.95 1.39/1.29 1.16/1.18 1.76/1.65 0.62/0.64 094/0.87 0.59/0.61 0.89/0.83 0.31/0.32 0.47/0.43 202 213 135 142 67 70 435 456 288 302 144 150
tpo
ns
tpo
ns
tpv tpv tpv tpv tpv tpv tps tps tps tdit tdit tdit trfi tpi tpi
ns ns ns ns ns ns V/ns V/ns V/ns mA/ns mA/ns mA/ns ns ns
1
--
2
3
0.11/0.12 0.16/0.20 0.87/1.08 1.37/1.62 1.68/1.89 2.18/2.42
4
Note: 1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 3.6 V and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 37
3.5.3.3
DDR_TYPE = 10 Max Setting I/O AC Parameters and Requirements
Table 25. AC Parameters for DDR2 I/O
Parameter Symbol Fduty f tpr tpo tpo tpv tpv tps tdit trfi tpi tpi Load Condition -- -- 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.0 pF 1.0 pF 1.0 pF Min. Rise/Fall 40 -- 0.53/0.52 1.01/0.98 0.93/1.25 1.26/1.54 1.01/1.17 1.27/1.53 1.30/1.19 1.62/1.54 1.39/1.27 1.64/1.55 0.86/0.98 0.46/054 65 70 0.07/0.08 0.83/0.99 1.65/1.81 Typ. 50 -- Max. Rise/Fall 60 133 Units % MHz ns ns ns ns ns V/ns mA/ns ns ns ns Notes -- -- 1 1 1 1 1 2 3 4
Table 25 shows AC parameters for DDR2 I/O.
Duty cycle Clock frequency Output pad transition times Output pad propagation delay, 50%-50% Output pad propagation delay, 40%-60% Output enable to output valid delay, 50%-50% Output enable to output valid delay, 40%-60% Output pad slew rate Output pad dI/dt Input pad transition times Input pad propagation delay, 50%-50% Input pad propagation delay, 40%-60%
0.80/0.72 1.19/1.04 1.49/1.34 2.21/1.90 1.56/1.70 2.52/2.53 2.07/2.19 3.29/3.24 1.60/1.75 2.49/2.52 2.00/2.14 3.11/3.10 2.17/1.81 3.35/2.84 2.56/2.29 3.35/2.54 2.13/1.86 3.38/2.83 2.62/2.23 4.14/2.38 1.35/1.5 2.15/2.19 0.72/0.81 1.12/1.16 157 167 373 396
0.10/0.12 0.17/0.20 1.23/1.49 1.79/2.04 2.05/2.31 2.60/2.84
Note: 1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.9 V and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.9 V and -40 C. Input transition time from pad is 5 ns (20%-80%).
i.MX25 Applications Processor for Automotive Products, Rev. 1 38 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
3. Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3.6 V and -40 C. Input transition time from pad is 5 ns (20%-80%).
Table 26 shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.
Table 26. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O
Parameter Duty cycle Clock frequency Output pad transition times Output pad propagation delay, 50%-50% input signals and crossing of output signals Output pad propagation delay, 40%-60% input signals and crossing of output signals Output enable to output valid delay, 50%-50% Output enable to output valid delay, 40%-60% Output pad slew rate Output pad dI/dt Input pad transition times Input pad propagation delay, 50%-50% Input pad propagation delay, 40%-60% Symbol Fduty f tpr tpo tpo tpv tpv tps tdit trfi tpi tpi Load Condition -- -- 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 25 pF 50 pF 1.0 pF 1.0 pF 1.0 pF Min. Rise/Fall 40 -- 0.53/0.52 1.01/0.98 1.3/1.21 1.59/1.5 1.47/1.38 1.75/1.67 1.32/1.28 1.66/1.65 1.40/1.37 1.67/1.66 0.86/0.98 0.46/054 72 77 0.07/0.08 0.89/0.87 1.71/1.69 Typ. 50 -- 0.80/0.72 1.49/1.34 1.97/1.84 2.37/2.24 Max. Rise/Fall 60 133 1.19/1.04 2.21/1.90 2.91/2.71 3.48/3.28 Units % MHz ns ns ns ns ns V/ns mA/ns ns ns ns Notes -- -- 1 1 1 1 1 2 3 4
2.13/2.00 3.072/2.87 2.54/2.40 3.65/3.45 2.11/2.00 2.61/2.50 2.16/2.06 2.56/2.45 1.35/1.5 0.72/0.81 172 183 0.10/0.12 1.41/1.37 2.22/2.18 3.31/3.12 4.06/3.81 3.30/3.13 3.89/3.67 2.15/2.19 1.12/1.16 400 422 0.17/0.20 2.16/2.07 2.98/2.88
Note: 1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.9 V and -40 C. Input transition time from core is 1 ns (20%-80%). 2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge. 3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and -40 C. 4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.9 V and -40 C. Input transition time from pad is 5 ns (20%-80%).
Table 27 shows the AC requirements for DDR2 I/O.
Table 27. AC Requirements for DDR2 I/O
Parameter1 AC input logic high AC input logic low AC differential input voltage2 AC differential cross point voltage for input
3 4
Symbol VIH(ac) VIL(ac) Vid(ac) Vix(ac) Vox(ac)
Min. OVDD/2 + 0.25 -0.3 0.5 OVDD/2-0.175 OVDD/2-0.125
Max. OVDD + 0.3 OVDD/2 - 0.25 OVDD + 0.6 OVDD/2 + 0.175 OVDD/2 + 0.125
Units V V V V V
AC differential cross point voltage for output
1
Note that the Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in this document.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 39
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2
3.6
Module Timing and Electrical Parameters
This section contains the timing and electrical parameters for i.MX25 modules.
3.6.1
1-Wire Timing Parameters
Figure 7 shows the reset and presence pulses (RPP) timing for 1-Wire, and Table 28 lists the RPP timing parameters.
1-Wire Tx "Reset Pulse" 1-Wire bus (OWIRE_LINE) 1-Wire Memory Device "Presence Pulse" OW2
OW1
OW3 OW4
Figure 7. 1-Wire RPP Timing Diagram Table 28. RPP Sequence Delay Comparisons Timing Parameters
ID OW1 OW2 OW3 OW4 Parameters Reset Time Low Presence Detect High Presence Detect Low Reset Time High Symbol tRSTL tPDH tPDL tRSTH Min. 480 15 60 480 Typ. 511 -- -- 512 Max. -- 60 240 -- Units us us us us
Figure 8 shows write 0 sequence timing, and Table 29 describes the timing parameters (OW5-OW6) that are shown in the figure.
OW6 1-Wire bus (OWIRE_LINE)
OW5
Figure 8. Write 0 Sequence Timing Diagram
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Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the "true" input signal and Vcp is the "complementary" input signal. The minimum value is equal to Vih(ac)-Vil(ac) 3 The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross. 4 The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross. Cload = 25 pF.
Table 29. WR0 Sequence Timing Parameters
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ID OW5 OW6 Write 0 Low Time Transmission Time Slot Parameter Symbol tWR0_low tSLOT Min. 60 OW5 Typ. 100 117 Max. 120 120 Units s s
Figure 9 and Figure 10 show write 1 and read sequence timing, respectively. Table 30 describes the timing parameters (OW7-OW8) that are shown in the figure.
OW8 1-Wire bus (OWIRE_LINE)
OW7
Figure 9. Write 1 Sequence Timing Diagram
OW8 1-Wire bus (OWIRE_LINE)
OW7 OW9
Figure 10. Read Sequence Timing Diagram Table 30. WR1 /RD Timing Parameters
ID OW7 OW8 OW9 Parameter Write 1 / read low time Transmission time slot Release time Symbol tLOW1 tSLOT tRELEASE Min. 1 60 15 Typ. 5 117 -- Max. 15 120 45 Units s s s
3.6.2
ATA Timing Parameters
Table 31 shows parameters used to specify the ATA timing. These parameters depend on the implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 41
Table 31. Timing Parameters
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Name T ti_ds Bus clock period Set-up time ata_data to ata_iordy edge (UDMA-in only) UDMA0 UDMA1 UDMA2,UDMA3 UDMA4 UDMA5 ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only) UDMA0,UDMA1,UDMA2,UDMA3,UDMA4 UDMA5 Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en Set-up time ata_data to bus clock L-to-H Set-up time ata_iordy to bus clock H-to-L Hold time ata_iordy to bus clock H-to-L Maximum difference in propagation delay bus clock L-to-H to any of the following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Maximum difference in buffer propagation delay for any of the following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Maximum difference in buffer propagation delay for any of the following signals ata_iordy, ata_data (read) Maximum buffer propagation delay cable propagation delay for ata_data cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack Maximum difference in cable propagation delay between ata_iordy and ata_data (read) Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) Maximum difference in cable propagation delay without accounting for ground bounce 15 ns 10 ns 7 ns 5 ns 4 ns 5.0 ns 4.6 ns 12.0 ns Description Value/Contributing Factor Peripheral clock frequency
tco
tsu tsui thi tskew1
8.5 ns 8.5 ns 2.5 ns 7 ns
tskew2
Transceiver
tskew3 tbuf tcable1 tcable2 tskew4 tskew5
Transceiver Transceiver Cable Cable Cable Cable
tskew6
Cable
i.MX25 Applications Processor for Automotive Products, Rev. 1 42 Freescale Semiconductor
3.6.2.1
PIO Mode Timing Parameters
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Figure 11 shows a timing diagram for PIO read mode.
t1 ADDR (See note 1) t5 DIOR READ Data(15:0) IORDY IORDY trd1 tA t6 t2r t9
Figure 11. PIO Read Mode Timing
To meet PIO read mode timing requirements, a number of timing parameters must be controlled. Table 32 shows timing parameters and their determining relations, and indicates parameters that can be adjusted to meet required conditions.
Table 32. Timing Parameters for PIO Read Mode
PIO Read ATA Mode Timing Parameter Parameter1 t1 t2 t9 t5 t6 tA trd t1 t2r t9 t5 t6 tA trd1 Relation t1(min.) = time_1 x T - (tskew1 + tskew2 + tskew5) t2(min.) = time_2r x T - (tskew1 + tskew2 + tskew5) t9(min.) = time_9 x T - (tskew1 + tskew2 + tskew6) t5(min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 0 tA(min.) = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2 x tbuf) trd1(max.) = (-trd) + (tskew3 + tskew4) trd1(min.) = (time_pio_rdx - 0.5) x T - (tsu + thi) (time_pio_rdx - 0.5) x T > tsu + thi + tskew3 + tskew4 t0(min.) = (time_1 + time_2 + time_9) x T Adjustable Parameter time_1 time_2r time_9 If not met, increase time_2 -- time_ax time_pio_rdx
t0
1
--
time_1, time_2r, time_9
See Figure 11.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 43
Figure 12 gives timing waveforms for PIO write mode.
ADDR (See note 1) DIOR DIOW buffer_en Write Data(15:0) ton tA IORDY IORDY tB t4 toff t1
Figure 12. PIO Write Mode Timing
To meet PIO write mode timing requirements, a number of timing parameters must be controlled. Table 33 shows timing parameters and their determining relations, and indicates parameters that can be adjusted to meet required conditions.
Table 33. Timing Parameters for PIO Write Mode
PIO Write ATA Mode Timing Parameter Parameter1 t1 t2 t9 t3 t4 tA t0 -- --
1
Relation t1(min.) = time_1 x T - (tskew1 + tskew2 + tskew5) t2(min.) = time_2w x T - (tskew1 + tskew2 + tskew5) t9(min.) = time_9 x T - (tskew1 + tskew2 + tskew6) t3(min.) = (time_2w - time_on) x T - (tskew1 + tskew2 +tskew5) t4(min.) = time_4 x T - tskew1 tA = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2 x tbuf) t0(min.) = (time_1 + time_2 + time_9) x T Avoid bus contention when switching buffer on by making ton long enough Avoid bus contention when switching buffer off by making toff long enough
Adjustable Parameter(s) time_1 time_2w time_9 if not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 -- --
t1 t2w t9 -- t4 tA -- -- --
See Figure 12.
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t1
t2w
t9
3.6.2.2
Multiword DMA (MDMA) Mode Timing
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Figure 13 and Figure 14 show the timing for MDMA read and write modes, respectively.
tk1 DMARQ ADDR (See note 1) DMACK DIOR tm READ Data(15:0) td tk tkjn
te tgr
tfr
Figure 13. MDMA Read Mode Timing
tk1 DMARQ ADDR (See note 1) DMACK buffer_en DIOW tm ton td1 Write Data(15:0) tk td tkjn toff
Figure 14. MDMA Write Mode Timing
To meet timing requirements, a number of timing parameters must be controlled. See Table 34 for details on timing parameters for MDMA read and write modes.
Table 34. Timing Parameters for MDMA Read and Write Modes
ATA Parameter tm, ti td tk t0 tg(read) tf(read) tg(write) MDMA Read1 and Write2 Timing Parameters tm td, td1 tk -- tgr tfr -- Adjustable Parameter(s) time_m time_d time_k time_d, time_k time_d -- time_d
Relation
tm(min.) = ti(min.) = time_m x T - (tskew1 + tskew2 + tskew5) td1(min.) = td(min.) = time_d x T - (tskew1 + tskew2 + tskew6) tk(min.) = time_k x T - (tskew1 + tskew2 + tskew6) t0(min.) = (time_d + time_k) x T tgr(min.-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min.-drive) = td - te(drive) tfr(min.-drive) =0 k tg(min.-write) = time_d x T -(tskew1 + tskew2 + tskew5)
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 45
Table 34. Timing Parameters for MDMA Read and Write Modes (continued)
Adjustable Parameter(s) time_k time_d, time_k3 time_jn --
Relation
tf(write) tL tn, tj --
1 2
-- -- tkjn ton toff
tf(min.-write) = time_k x T - (tskew1 + tskew2 + tskew6) tL(max.) = (time_d + time_k-2) x T - (tsu + tco + 2 x tbuf + 2 x tcable2) tn= tj= tkjn = (max.(time_k,. time_jn) x T - (tskew1 + tskew2 + tskew6) ton = time_on x T - tskew1 toff = time_off x T - tskew1
See Figure 13. See Figure 14. 3 tk1 in the UDMA figures equals (tk -2 x T).
3.6.2.3
Ultra DMA (UDMA) Mode Timing
UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA in- and out-transfers are provided. 3.6.2.3.1 UDMA In-Transfer Timing
Figure 15 shows the timing for UDMA in-transfer start.
tack ADDR DMARQ DMACK tenv DIOR DIOW tc1 IORDY DATA READ tds tdh tc1
Figure 15. Timing for UDMA In-Transfer Start
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MDMA Read1 and Write2 ATA Parameter Timing Parameters
Figure 16 shows the timing for host-terminated UDMA in-transfer.
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47
ADDR DMARQ DMACK DIOR DIOW tc1 IORDY DATA READ tds tdh tzah tzah DATA WRITE buffer_en ton tdzfs tcvh toff tmli tc1 tx1 tmli trp tack
Figure 16. Timing for Host-Terminated UDMA In-Transfer
Figure 17 shows timing for device-terminated UDMA in-transfer.
ADDR DMARQ DMACK DIOR DIOW tc1 IORDY DATA READ tds tdh tzah tzah DATA WRITE buffer_en ton tdzfs tcvh toff tmli tc1 tss1 tli5 tmli tack
Figure 17. Timing for Device-Terminated UDMA Transfer
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor
Timing parameters for UDMA in-burst are listed in Table 35.
Table 35. Timing Parameters for UDMA In-Burst
ATA Parameter tack tenv tds tdh tcyc trp -- tmli tzah tdzfs tcvh --
1
Spec. Parameter tack tenv tds1 tdh1 tc1 trp tx11 tmli1 tzah tdzfs tcvh ton toff
Value tack(min.) = (time_ack x T) - (tskew1 + tskew2) tenv(min.) = (time_env x T) - (tskew1 + tskew2) tenv(max.) = (time_env x T) + (tskew1 + tskew2) tds - (tskew3) - ti_ds > 0 tdh - (tskew3) -ti_dh > 0 (tcyc - tskew) > T trp(min.) = time_rp x T - (tskew1 + tskew2 + tskew6) (time_rp x T) - (tco + tsu + 3T + 2 x tbuf + 2 x tcable2) > trfs (drive) tmli1(min.) = (time_mlix + 0.4) x T tzah(min.) = (time_zah + 0.4) x T tdzfs = (time_dzfs x T) - (tskew1 + tskew2) tcvh = (time_cvh x T) - (tskew1 + tskew2) ton = time_on x T - tskew1 toff = time_off x T - tskew1
Required Conditions time_ack time_env tskew3, ti_ds, ti_dh should be low enough T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh --
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. Make ton and toff big enough to avoid bus contention.
3.6.2.4
UDMA Out-Transfer Timing
Figure 18 shows the timing for start of UDMA out-transfer.
tack ADDR DMARQ DMACK tenv DIOW DIOR buffer_en ton DATA WRITE IORDY tli1 trfs1 tcyc tdzfs tdvs tdvh tdvs tcyc
Figure 18. Timing for UDMA Out-Transfer Start
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Figure 19 shows timing for host-terminated UDMA out-transfer.
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49
ADDR DMARQ DMACK DIOW DIOR tcyc tli2 tcyc1 DATA WRITE IORDY buffer_en tli3 tdzfs_mli tcvh toff tss tack
Figure 19. Timing for Host-Terminated UDMA Out-Transfer
Timing parameters for UDMA out-bursts are listed in Table 36.
Table 36. Timing Parameters UDMA Out-Bursts
ATA Parameter tack tenv tdvs tdvh tcyc t2cyc trfs1 -- tss tmli tli tli tli tcvh -- Spec Parameter tack tenv tdvs tdvh tcyc -- trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff Value tack(min.) = (time_ack x T) - (tskew1 + tskew2) tenv(min.) = (time_env x T) - (tskew1 + tskew2) tenv(max.) = (time_env x T) + (tskew1 + tskew2) tdvs = (time_dvs x T) - (tskew1 + tskew2) tdvs = (time_dvh x T) - (tskew1 + tskew2) tcyc = time_cyc x T - (tskew1 + tskew2) t2cyc = time_cyc x 2 x T trfs = 1.6 x T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs x T - (tskew1) tss = time_ss x T - (tskew1 + tskew2) tdzfs_mli =max.(time_dzfs, time_mli) x T - (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh x T) - (tskew1 + tskew2) ton = time_on x T - tskew1 toff = time_off x T - tskew1 How to Meet? time_ack time_env time_dvs time_dvh time_cyc time_cyc -- time_dzfs time_ss -- -- -- -- time_cvh --
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor
3.6.3
Digital Audio Mux (AUDMUX) Timing
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The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between internal serial interfaces (SSI and SAP) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is governed by the SSI modules. For more information, see Section 3.6.17, "Synchronous Serial Interface (SSI) Timing."
3.6.4
CMOS Sensor Interface (CSI) Timing
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as dumb or smart as follows: * Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync (HSYNC)) and output-only Bayer and statistics data. * Smart sensors support CCIR656 video decoder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats). The following subsections describe the CSI timing in gated and ungated clock modes.
3.6.4.1
Gated Clock Mode Timing
Figure 20 and Figure 21 shows the gated clock mode timings for CSI, and Table 37 describes the timing parameters (P1-P7) shown in the figures. A frame starts with a rising/falling edge on VSYNC, then HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted.
VSYNC P1 HSYNC P7 P2 PIXCLK P3 P4 P5 P6
DATA[15:0]
Figure 20. CSI Gated Clock Mode--Sensor Data at Falling Edge, Latch Data at Rising Edge
i.MX25 Applications Processor for Automotive Products, Rev. 1 50 Freescale Semiconductor
VSYNC P1 HSYNC P7 P2 PIXCLK P3 P4 P6 P5
DATA[15:0]
Figure 21. CSI Gated Clock Mode--Sensor Data at Rising Edge, Latch Data at Falling Edge Table 37. CSI Gated Clock Mode Timing Parameters
ID P1 P2 P3 P4 P5 P6 P7 Parameter CSI VSYNC to HSYNC time CSI HSYNC setup time CSI DATA setup time CSI DATA hold time CSI pixel clock high time CSI pixel clock low time CSI pixel clock frequency Symbol tV2H tHsu tDsu tDh tCLKh tCLKl fCLK Min. 67.5 1 1 1.2 10 10 -- Max. -- -- -- -- -- -- 48 10% Units ns ns ns ns ns ns MHz
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3.6.4.2
Ungated Clock Mode Timing
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Figure 22 shows the ungated clock mode timings of CSI, and Table 38 describes the timing parameters (P1-P6) that are shown in the figure. In ungated mode the VSYNC and PIXCLK signals are used, and the HSYNC signal is ignored.
VSYNC P1 P4 PIXCLK P2 P3
P6 P5
DATA[15:0]
Figure 22. CSI Ungated Clock Mode--Sensor Data at Falling Edge, Latch Data at Rising Edge Table 38. CSI Ungated Clock Mode Timing Parameters
ID P1 P2 P3 P4 P5 P6 Parameter CSI VSYNC to pixel clock time CSI DATA setup time CSI DATA hold time CSI pixel clock high time CSI pixel clock low time CSI pixel clock frequency Symbol tVSYNC tDsu tDh tCLKh tCLKl fCLK Min. 67.5 1 1.2 10 10 -- Max. -- -- -- -- -- 48 10% Units ns ns ns ns ns MHz
3.6.5
Configurable Serial Peripheral Interface (CSPI) Timing
Figure 23 and Figure 24 provide CSPI master and slave mode timing diagrams, respectively. Table 39 describes the timing parameters (t1-t14) that are shown in the figures. The values shown in timing diagrams were tested using a worst-case core voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad voltage of 1.65 V.
i.MX25 Applications Processor for Automotive Products, Rev. 1 52 Freescale Semiconductor
t7 SSn (output) t8
t5
t9
t6 RDY (input) SCLK (output) MOSI t12 MISO t13 t1 t2 t3
t10
t11 t4 t4
Figure 23. CSPI Master Mode Timing Diagram
t7' SSn (input) t6' t1' SCLK (input) MISO t12 MOSI t13 t2' t3' t5'
t10
t11 t4 t4 t14
t14
Figure 24. CSPI Slave Mode Timing Diagram Table 39. CSPI Interface Timing Parameters
ID t1 t2 t3 t1' t2' t3' Parameter Description CSPI master SCLK cycle time CSPI master SCLK high time CSPI master SCLK low time CSPI slave SCLK cycle time CSPI slave SCLK high time CSPI slave SCLK low time Symbol tclko tclkoH tclkoL tclki tclkiH tclkiL Minimum 60.2 22.65 22.47 60.2 30.1 30.1 Maximum -- -- -- -- -- -- Units ns ns ns ns ns ns
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 53
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Table 39. CSPI Interface Timing Parameters (continued)
ID t4 t5 t5' t6 t6' t7 t7' t8 t9 t10 Parameter Description CSPI SCLK transition time SSn output pulse width SSn input pulse width SSn output asserted to first SCLK edge (SS output setup time) SSn input asserted to first SCLK edge (SS input setup time) CSPI master: Last SCLK edge to SSn negated (SS output hold time) CSPI slave: Last SCLK edge to SSn negated (SS input hold time) CSPI master: CSPI1_RDY low to SSn asserted (CSPI1_RDY setup time) CSPI master: SSn negated to CSPI1_RDY low Output data setup time Symbol tpr1 tWsso tWssi tSsso tSssi tHsso tHssi tSrdy tHrdy tSdatao Minimum 2.6 2Tsclk2 +T wait
3
Maximum 8.5 -- -- -- -- -- -- 5Tper -- --
Units ns -- -- -- -- -- ns -- ns --
Tper4 3Tsclk Tper 2Tsclk 30 2Tper 0 (tclkoL or tclkoH or tclkiL or tclkiH) - Tipg5 tclkoL or tclkoH or tclkiL or tclkiH Tipg + 0.5 0 0
t11 t12 t13 t14
1 2
Output data hold time Input data setup time Input data hold time Pause between data word
tHdatao tSdatai tHdatai tpause
-- -- -- --
-- ns ns ns
The output SCLK transition time is tested with 25 pF drive. Tsclk = CSPI clock period 3T wait = Wait time, as specified in the sample period control register 4T per = CSPI reference baud rate clock period (PERCLK2) 5T ipg = CSPI main clock IPG_CLOCK period
3.6.6
External Memory Interface (EMI) Timing
The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash controller (NFC), and wireless external interface module (WEIM). The following subsections give timing information for these submodules.
3.6.6.1
3.6.6.1.1
ESDCTL Electrical Specifications
SDRAM Memory Controller
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces SDRAM.
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SD1 SDCLK SD2 SD3
SD4 CS SD5 RAS SD4
SD5 CAS SD4
SD4 SD5 WE SD6 SD7 ADDR ROW/BA
SD5
COL/BA SD8 SD10 SD9 Data
DQ
DQM
SD4
Note: CKE is high during the read/write cycle.
SD5
Figure 25. SDRAM Read Cycle Timing Diagram Table 40. DDR/SDR SDRAM Read Cycle Timing Parameters
ID SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 Parameter SDRAM clock high-level width1 SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address setup time Address hold time SDRAM access time
1
Symbol tCH tCL tCK tCMS tCMH tAS tAH tAC
Min. 3.4 3.4 7.5 2.0 1.8 2.0 1.8 --
Max. 4.1 4.1 -- -- -- -- -- 6.47
Unit ns ns ns ns ns ns ns ns
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SDCLK
Table 40. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID SD9 SD10
1 2
Parameter Data out hold time2 Active to read/write command period
Symbol tOH tRC
Min. 1.2 10
Max. -- --
Unit ns clock
SD1 + SD2 does not exceed 7.5 ns for 133 MHz. Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Table 44 and Table 45.
SD1 SDCLK SDCLK SD2 SD3 SD4 CS SD5 RAS SD11 CAS SD5 SD4 SD4
SD4
WE SD5 SD7 SD6 ADDR BA ROW / BA SD13 DQ DATA COL/BA SD12
SD5
SD14
DQM
Figure 26. SDR SDRAM Write Cycle Timing Diagram
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Table 41. SDR SDRAM Write Timing Parameters
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
ID SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD11 SD12 SD13 SD14
1
Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM, CKE setup time CS, RAS, CAS, WE, DQM, CKE hold time Address setup time Address hold time Precharge cycle period
1 1
Symbol tCH tCL tCK tCMS tCMH tAS tAH tRP tRCD tDS tDH
Min. 3.4 3.4 7.5 2.0 1.8 2.0 1.8 1 1 2.0 1.3
Max. 4.1 4.1 -- -- -- -- -- 4 8 -- --
Unit ns ns ns ns ns ns ns clock clock ns ns
Active to read/write command delay Data setup time Data hold time
SD11 and SD12 are determined by SDRAM controller register settings.
SD1 SDCLK SDCLK SD2 SD3 CS
RAS SD11 CAS SD10 WE SD10
SD7 SD6 ADDR BA ROW/BA
Figure 27. SDRAM Refresh Timing Diagram
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Table 42. SDRAM Refresh Timing Parameters
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
ID SD1 SD2 SD3 SD6 SD7 SD10 SD11
1
Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 Auto precharge command period
1
Symbol tCH tCL tCK tAS tAH tRP tRC
Min. 3.4 3.4 7.5 1.8 1.8 1 2
Max. 4.1 4.1 -- -- -- 4 20
Unit ns ns ns ns ns clock clock
SD10 and SD11 are determined by SDRAM controller register settings.
SDCLK CS
RAS
CAS
WE
ADDR
BA
CKE
SD16
SD16
Don't care
Figure 28. SDRAM Self-Refresh Cycle Timing Diagram
NOTE The clock continues to run unless CKE is low. Then the clock is stopped in low state.
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Table 43. SDRAM Self-Refresh Cycle Timing Parameters
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ID SD16 Parameter CKE output delay time Symbol tCKS Min. 1.8 Max. -- Unit ns
3.6.6.1.2
Mobile DDR SDRAM-Specific Parameters
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces with the mobile DDR SDRAM.
SDCLK SDCLK SD19 DQS (output) SD17 DQ (output) Data Data SD20
SD18
SD17 Data Data
SD18 Data Data Data Data
DQM (output) SD17
DM
DM
DM SD17
DM
DM SD18
DM
DM
DM
SD18
Figure 29. Mobile DDR SDRAM Write Cycle Timing Diagram Table 44. Mobile DDR SDRAM Write Cycle Timing Parameters1
ID SD17 SD18 SD19 SD20
1
Parameter DQ and DQM setup time to DQS DQ and DQM hold time to DQS Write cycle DQS falling edge to SDCLK output delay time Write cycle DQS falling edge to SDCLK output hold time
Symbol tDS tDH tDSS tDSH
Min. 0.95 0.95 1.8 1.8
Max. -- -- -- --
Unit ns ns ns ns
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 59
SDCLK SDCLK SD23 DQS (input) SD22 SD21 DQ (input) Data Data Data Data Data Data Data Data
Figure 30. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 45. Mobile DDR SDRAM Read Cycle Timing Parameters
ID Parameter Symbol tDQSQ tQH tDQSCK Min. Max. Unit -- 2.3 -- 0.85 -- 6.7 ns ns ns
SD21 DQS - DQ Skew (defines the data valid window in read cycles related to DQS) SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge
3.6.6.1.3
DDR2 SDRAM-Specific Parameters
The following diagrams and tables specify timing related to the SDRAMC module, which interfaces with DDR2 SDRAM.
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SDCLK SDCLK
DDR4
CS
DDR2 DDR3
DDR4
RAS
DDR5
DDR5 DDR4
CAS
DDR4
DDR5
WE
DDR5
CKE
DDR6
ADDR ROW/BA
DDR4 DDR7
COL/BA
Figure 31. DDR2 SDRAM Basic Timing Parameters
Table 46 provides values for a command/address slew rate of 1 V/ns and an SDCLK, SDCLK_B differential slew rate of 2 V/ns. For additional values, use Table 47, "tlS, tlH Derating Values for DDR2-400, DDR2-533."
Table 46. DDR2 SDRAM Timing Parameter Table
DDR2-400 ID DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 Parameter SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, CKE, WE setup time CS, RAS, CAS, CKE, WE hold time Address output setup time Address output hold time Symbol Min. tCH tCL tCK tIS tIH tIS tIH 0.45 0.45 7.5 0.35 0.475 0.35 0.475 Max. 0.55 0.55 8 -- -- -- -- tCK tCK ns ns ns ns ns Unit
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DDR1
Table 46 shows values for a command/address slew rate of 1 V/ns and an SDCLK, SDCLK_B differential slew rate of 2 V/ns. Table 47 shows additional values for DDR2-400 and DDR2-533.
Table 47. tlS, tlH Derating Values for DDR2-400, DDR2-533 CK, CK Differential Slew Rate
Command/ Address Slew Rate (V/Ns) tlS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 +187 +179 +167 +150 +125 +83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 -1450 2.0 V/ns tlH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 tlS +217 +209 +197 +180 +155 +113 +30 +19 +5 -13 -37 -80 -145 -255 -320 -495 -770 -1420 1.5 V/ns tlH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 tlS +247 +239 +227 +210 +185 +143 +60 +49 +35 +17 -7 -50 -115 -225 -290 -465 -740 -1390 1.0 V/ns tlH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps Units
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SDCLK_B
DDR21 DDR22 DDR18
Data Data
DQS (output)
DDR17
DDR17
Data
DDR23 DDR18
DDR20
DDR19
DQ (output) DQM (output)
DDR17
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DDR18
DDR17
DDR18
Figure 32. DDR2 SDRAM Write Cycle Timing Diagram Table 48. DDR2 SDRAM Write Cycle Parameter Table
DDR2-400 ID DDR17 DDR18 DDR19 DDR20 DDR21 DDR22 DDR23
1
Parameter DQ & DQM setup time to DQS (single-ended strobe)1 DQ & DQM hold time to DQS (single-ended strobe)
1
Symbol Min. tDS1(base) tDH1(base) tDSS tDSH tDQSS tDQSH tDQSL 0.025 0.025 0.2 0.2 -0.25 0.35 0.35 Max. -- -- -- -- 0.25 -- --
Unit ns ns tCK tCK tCK tCK tCK
Write cycle DQS falling edge to SDCLK output setup time Write cycle DQS falling edge to SDCLK output hold time DQS latching rising transitions to associated clock edges DQS high-level width DQS low-level width
These values are for a DQ/DM slew rate of 1 V/ns and a DQS slew rate of 1 V/ns. For additional values use Table 49, "DtDS1, DtDH1 Derating Values for DDR2-400, DDR2-533."
Table 49. tDS1, tDH1 Derating Values for DDR2-400, DDR2-5331,2,3
DQS Single-Ended Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ns 0.9 V/ns 0.8 V/ns 0.7 V/ns tD H1 0.6 V/ns tD S1 tD H1 0.5 Vns tD S1 tD H1 0.4 V/ns tD S1 tD H1
tD tD tD tD tD tD tD tD tD tD tD S1 H1 S1 H1 S1 H1 S1 H1 S1 H1 S1
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SDCLK
Table 49. tDS1, tDH1 Derating Values for DDR2-400, DDR2-5331,2,3 (continued)
DQS Single-Ended Slew Rate 2.0 188 1.5 146 1.0 63 0.9 DQ Slew Rate 0.8 V/ns 0.7 0.6 0.5 0.4
1 2
188 167 146 125 167 125 125 125 -- -- -- -- -- -- 42 31 -- -- -- -- -- 83 69 -- -- -- -- -- 83 0
63 42 0
-- 81 -2
-- 43 1
-- -- -7
-- -- -13
-- -- --
-- -- -- -45 -62 -85
-- -- -- -- -60
-- -- -- -- -86
-- -- -- -- --
-- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-11 -14 -13 -13 -18 -27 -29 -25 -31 -27 -30 -32 -44 -43 -- -- -- -- -- -- -- -- -45 -53 -50 -67 -61 -- -- -- -- -- --
-78 -109 -108 -152
-74 -96 -85 -114 -102 -138 -132 -181 -183 -246 -- -- -- -- -128 -156 -145 -180 -175 -223 -226 -288 -- -- -210 -243 -240 -286 -291 -351
All units in `ps'. Test conditions are at capacitance=15pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls. 3 SDRAM CLK and DQS related parameters are measured from the 50% point. That is, high is defined as 50% of the signal value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock).
SDCLK SDCLK_B DQS (input)
DDR26 DDR25 DDR24
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram Table 50. DDR2 SDRAM Read Cycle Parameter Table1,2
DDR2-400 ID Parameter Symbol Min. Max. DDR24 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS) DDR25 DQS DQ in HOLD time from DQS
3
Unit -- 2.925 -0.5 0.35 -- 0.5 ns ns ns
tDQSQ tQH tDQSCK
DDR26 DQS output access time from SDCLK posedge
1
Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls.
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2
3.6.6.2
NAND Flash Controller (NFC) Timing
The i.MX25 NFC supports normal timing mode, using two Flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 34 through Figure 37 depicts the relative timing between NFC signals at the module level for different operations under normal mode. Table 51 describes the timing parameters (NF1-NF17) that are shown in the figures.
NFCLE NF1 NF3 NFCE NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Command NF7 NF2 NF4
Figure 34. Command Latch Cycle Timing Diagram
NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[7:0] Address NF7 NF4
Figure 35. Address Latch Cycle Timing Diagram
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SDRAM CLK and DQS-related parameters are measured from the 50% point. That is, high is defined as 50% of the signal value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock). 3 The value was calculated for an SDCLK frequency of 133 MHz, by the formula tQH = tHP - tQHS = min. (tCL,tCH) - tQHS = 0.45*tCK - tQHS = 0.45 * 7.5 - 0.45 = 2.925 ns
NFCLE NF1 NF3 NFCE NF10 NF11 NF5 NFWE NF6 NFALE NF8 NF9 NFIO[15:0] Data to NF NF7
Figure 36. Write Data Latch Cycle Timing Diagram
NFCLE
NFCE NF14 NF15 NF13 NFRE NF16 NFRB NF12 NFIO[15:0] Data from NF NF17
Figure 37. Read Data Latch Cycle Timing Diagram Table 51. NFC Timing Parameters1
Timing T = NFC Clock Cycle Min. NF1 NF2 NF3 NF4 NFCLE setup time NFCLE hold time NFCE setup time NFCE hold time tCLS tCLH tCS tCH T-1.0 ns T-2.0 ns 2T-5.0 ns 7T-5.0 ns Max. -- -- -- -- Example Timing for NFC Clock 33 MHz T = 30 ns Min. 29 28 55 205 Max. -- -- -- -- ns ns ns ns
ID
Parameter
Symbol
Unit
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Table 51. NFC Timing Parameters1 (continued)
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Timing T = NFC Clock Cycle Min. NF5 NF6 NF7 NF8 NF9 NF10 NF11 NF12 NF13 NF14 NF15 NF16 NF17
1
ID
Parameter
Symbol
Example Timing for NFC Clock 33 MHz T = 30 ns Min. 28.5 Max.
Unit
Max. T-1.5 ns
NF_WP pulse width NFALE setup time NFALE hold time Data setup time Data hold time Write cycle time NFWE hold time Ready to NFRE low NFRE pulse width READ cycle time NFRE high hold time Data setup on read Data hold on read
tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR T
ns -- -- -- -- ns ns ns ns ns ns -- -- -- -- -- -- ns ns ns ns ns ns
-- -- -- -- 2T T-2.5 ns
30 27 60 25 60 27.5
T-3.0 ns 2T ns T-5.0 ns
21T-10 ns 1.5T 2T 0.5T-2.5 ns N/A N/A
-- -- --
620 45 60 12.5 10 0
The Flash clock maximum frequency is 50 MHz.
NOTE For timing purposes, transition to signal high is defined as 80% of signal value; while signal low is defined as 20% of signal value. Timing for HCLK is 133 MHz. The internal NFC clock (Flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not related to the NFC clock.
3.6.6.3
Wireless External Interface Module (WEIM) Timing
Figure 38 depicts the timing of the WEIM module, and Table 52 describes the timing parameters (WE1-WE27) shown in the figure. All WEIM output control signals may be asserted and negated by internal clock relative to BCLK rising edge or falling edge according to corresponding assertion/negation control fields. Address always begins relative to BCLK falling edge, but may be ended on rising or falling edge in muxed mode according to the control register configuration. Output data begins relative to BCLK rising edge except in muxed mode, where rising or falling edge may be used according to the control register configuration. Input data, ECB and DTACK are all captured relative to BCLK rising edge.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 67
WEIM Output Timing
WE1
BCLK
WE2
...
WE3
WE4
Address CSx_B
WE5 WE7 WE9
WE6 WE8
RW_B OE_B
WE10
WE11
WE12
EBy_B LBA_B
WE13
WE14 WE16
WE15 WE17
Output Data
WEIM Input Timing
BCLK
WE18, WE19
Input Data
WE20, WE21 WE22, WE23
ECB_B
WE24, WE25 WE26
DTACK_B
WE27
Figure 38. WEIM Bus Timing Diagram Table 52. WEIM Bus Timing Parameters1
ID WE1 WE2 WE3 WE4 WE5 WE6 WE7 BCLK cycle time2 BCLK low-level width
2 2
Parameter
Min. 14.5 7 7 15 22 15 3.3
Max. -- -- -- 21 25 19 5
Unit ns ns ns ns ns ns ns
BCLK high-level width
Clock fall to address valid Clock rise/fall to address invalid Clock rise/fall to CSx_B valid Clock rise/fall to CSx_B invalid
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Table 52. WEIM Bus Timing Parameters1 (continued)
ID WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE18 WE19 WE20 WE21 WE22 WE23 WE24 WE25 WE26 WE27
1 2
Parameter Clock rise/fall to RW_B valid Clock rise/fall to RW_B invalid Clock rise/fall to OE_B valid Clock rise/fall to OE_B invalid Clock rise/fall to EBy_B valid Clock rise/fall to EBy_B invalid Clock rise/fall to LBA_B valid Clock rise/fall to LBA_B invalid Clock rise/fall to output data valid Clock rise to output data invalid Input data valid to clock rise, FCE=1 Input data valid to clock rise, FCE=0 Clock rise to input data invalid, FCE=1 Clock rise to input data invalid, FCE=0 ECB_B setup time, FCE=1 ECB_B setup time, FCE=0 ECB_B hold time, FCE=1 ECB_B hold time, FCE=0 DTACK_B setup time DTACK_B hold time
Min. 8 3 7 3.6 6 6 17.5 0 5 0 1 6.9 1 2.4 5 7.2 5 0 5.4 -3.2
Max. 12 8 12 5.5 11.5 10 20 1 10 2.5 -- -- -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
High is defined as 80% of signal value; low is defined as 20% of signal value. BCLK parameters are being measured from the 50% point. For example, high is defined as 50% of signal value and low is defined as 50% as signal value.
NOTE The test condition load capacitance was 25 pF. Recommended drive strength for all controls, address, and BCLK is maximum drive. Recommended drive strength for all controls, address and BCLK is maximum drive.
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Figure 39 through Figure 44 give examples of basic WEIM accesses to external memory devices with the timing parameters described in Table 52 for specific control parameter settings.
BCLK WE4 ADDR CS[x] RW WE14 LBA WE10 WE15 Last Valid Address WE6 V1 WE5 Next Address WE7
OE
WE11
WE12 EB[y]
WE13
WE21 DATA V1 WE19
Figure 39. Synchronous Memory Timing Diagram for Read Access--WSC=1
BCLK WE4 ADDR CS[x] Last Valid Address WE6 WE8 RW LBA OE WE12 WE13 WE17 DATA WE16 V1 WE14 WE15 V1 WE7 WE9 WE5 Next Address
EB[y]
Figure 40. Synchronous Memory Timing Diagram for Write Access-- WSC=1, EBWA=1, EBWN=1, LBN=1
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BCLK ADDR Last Valid Addr CS[x] RW WE14 WE15 WE11 WE6 Address V1 Address V2 WE7
LBA
OE EB[y]
WE10
WE12 WE24 WE24
WE13
ECB WE22 WE19 DATA WE18
V1 V1+2 Halfword Halfword
WE22 WE19
V2 Halfword V2+2 Halfword
WE18
Figure 41. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses-- WSC=2, SYNC=1, DOL=0
BCLK WE4 ADDR Last Valid Addr CS[x] WE6 Address V1 WE7 WE5
RW
WE8 WE14 WE15
WE9
LBA
OE EB[y] WE12 WE13
WE24 ECB WE22 WE17 DATA WE16 V1 WE16 WE17 V1+4 V1+8 V1+12
Figure 42. Synchronous Memory TIming Diagram for Burst Write Access-- BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1
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WE4
WE5
Address V1 WE16
Write Data WE7
CS[x]
WE6
RW
WE8 Write WE14 WE15
WE9
LBA
OE EB[y] WE12 WE13
Figure 43. Muxed A/D Mode Timing Diagram for Synchronous Write Access-- WSC=7, LBA=1, LBN=1, LAH=1
BCLK WE4 ADDR/ Last Valid Addr M_DATA WE6 CS[x] WE5 Address V1 WE20 Read Data WE18 WE7 RW WE14 LBA WE15
OE EB[y] WE12
WE10
WE11
WE13
Figure 44. Muxed A/D Mode Timing Diagram for Synchronous Read Access-- WSC=7, LBA=1, LBN=1, LAH=1, OEA=7
Figure 45 through Figure 49, and Table 49 help to determine timing parameters relative chip select (CS) state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing parameters mentioned above.
i.MX25 Applications Processor for Automotive Products, Rev. 1 72 Freescale Semiconductor
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WE4 ADDR/ Last Valid Addr M_DATA
BCLK
WE5
WE17
CS [x] WE31 ADDR RW WE39 LBA WE35 OE WE37 EB[y] DATA WE43 V1 WE38 WE44 WE36 WE40 Last Valid Address Address V1 WE32 Next Address
Figure 45. Asynchronous Memory Read Access
CS[x]
WE31 MAXDI
ADDR/ M_DATA WE LBA OE
WE37 WE39 WE35A
Addr. V1
WE32A
D(V1)
WE44 WE40
WE36 WE38
BE[y]
MAXCO
Figure 46. Asynchronous A/D Muxed Read Access (RWSC = 5)
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 73
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CS[x]
WE31 WE32
ADDR RW
Last Valid Address
WE33 WE39
Address V1
WE34 WE40
Next Address
LBA OE
WE45 WE46 WE42
BE[y] DATA
WE41
D(V1) Figure 47. Asynchronous Memory Write Access
CS[x]
WE31 WE41
ADDR/ M_DATA
WE33
Addr. V1
WE32A
D(V1)
WE34 WE42
RW
WE40A
LBA OE
WE39
WE45
WE46 WE42
BE[y]
Figure 48. Asynchronous A/D Mux Write Access
i.MX25 Applications Processor for Automotive Products, Rev. 1 74 Freescale Semiconductor
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CS [x] WE31 ADDR RW WE39 LBA WE35 OE WE37 EB[y] DATA WE43 WE48 DATA WE47 V1 WE38 WE44 WE36 WE40 Last Valid Address Address V1 WE32 Next Address
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Figure 49. DTACK Read Access
Table 53. WEIM Asynchronous Timing Parameters Relative Chip Select Table
Determination By Synchronous Measured Parameters1 WE4 - WE6 - CSA2 WE7 - WE5 - CSN3 Max (If 133 MHz is supported by SoC) 3 - CSA 3 - CSN --
Ref No.
Parameter
Min
Unit
WE31 WE32 WE32A( muxed A/D WE33 WE34 WE35 WE35A (muxed A/D) WE36 WE37 WE38 WE39 WE40
CS[x] valid to Address Valid Address Invalid to CS[x] invalid CS[x] valid to Address Invalid
-- --
ns ns ns
WE4 - WE7 + (LBN + LBA + 1 -3 + (LBN + LBA + - CSA2) 1 - CSA) WE8 - WE6 + (WEA - CSA) WE7 - WE9 + (WEN - CSN) WE10 - WE6 + (OEA - CSA) WE10 - WE6 + (OEA + RLBN + RLBA + ADH + 1 - CSA) WE7 - WE11 + (OEN - CSN) -- -- -- -3 + (OEA + RLBN + RLBA + ADH + 1 - CSA) -- -- -- -- --
CS[x] Valid to WE Valid WE Invalid to CS[x] Invalid CS[x] Valid to OE Valid CS[x] Valid to OE Valid
3 + (WEA - CSA) 3 - (WEN_CSN) 3 + (OEA - CSA) 3 + (OEA + RLBN + RLBA + ADH + 1 - CSA) 3 - (OEN - CSN) 3+ (RBEA4 - CSA)
ns ns ns ns
OE Invalid to CS[x] Invalid
ns ns ns ns ns
CS[x] Valid to BE[y] Valid (Read WE12 - WE6 + (RBEA - CSA) access) BE[y] Invalid to CS[x] Invalid (Read access) CS[x] Valid to LBA Valid LBA Invalid to CS[x] Invalid WE7 - WE13 + (RBEN - CSN) WE14 - WE6 + (LBA - CSA) WE7 - WE15 - CSN
3 - (RBEN5 - CSN) 3 + (LBA - CSA) 3 - CSN
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 75
Table 53. WEIM Asynchronous Timing Parameters Relative Chip Select Table (continued)
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Determination By Synchronous Measured Parameters1 Max (If 133 MHz is supported by SoC)
Ref No.
Parameter
Min
Unit
WE40A (muxed A/D) WE41
CS[x] Valid to LBA Invalid
WE14 - WE6 + (LBN + LBA + 1 -3 + (LBN + LBA + 3 + (LBN + LBA + 1 - - CSA) 1 - CSA) CSA) WE16 - WE6 - WCSA WE16 - WE6 + (WLBN + WLBA + ADH + 1 - WCSA) WE17 - WE7 - CSN MAXCO - MAXCSO + MAXDI -- -- 3 - WCSA 3 + (WLBN + WLBA + ADH + 1 - WCSA) 3 - CSN --
ns
CS[x] Valid to Output Data Valid
ns ns
WE41A CS[x] Valid to Output Data Valid (muxed A/D) WE42 WE43 Output Data Invalid to CS[x] Invalid Input Data Valid to CS[x] Invalid CS[x] Invalid to Input Data invalid CS[x] Valid to BE[y] Valid (Write access) BE[y] Invalid to CS[x] Invalid (Write access) DTACK Valid to CS[x] Invalid
-- MAXCO6 - MAXCSO 7 + MAXDI8 0 -- -- MAXCO6 - MAXCSO 7Note:Not e: + MAXDTI9 0
ns ns
WE44 WE45 WE46 WE47
0 WE12 - WE6 + (WBEA - CSA) WE7 - WE13 + (WBEN - CSN) MAXCO - MAXCSO + MAXDTI
-- 3 + (WBEA - CSA) -3 + (WBEN - CSN) --
ns ns ns ns
WE48
1 2 3 4 5 6 7 8 9
CS[x] Invalid to DTACK invalid
0
--
ns
For the value of parameters WE4-WE21, see column BCD = 0 in Table 52. CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles. CS Negation. This bit field determines when the CS signal is negated during read/write cycles. BE Assertion. This bit field determines when the BE signal is asserted during read cycles. BE Negation. This bit field determines when the BE signal is negated during read cycles. Output maximum delay from internal driving ADDR/control FFs to chip outputs. Output maximum delay from CS[x] internal driving FFs to CS[x] out. DATA maximum delay from chip input data to its internal FF. DTACK maximum delay from chip dtack input to its internal FF.
Note: All configuration parameters (CSA,CSN,WBEA,WBEN,LBA,LBN,OEN,OEA,RBEA & RBEN) are in cycle units.
i.MX25 Applications Processor for Automotive Products, Rev. 1 76 Freescale Semiconductor
3.6.7
Enhanced Serial Audio Interface (ESAI) Timing
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77
This section describes general timing requirements for ESAI, as well as the ESAI transmit and receive timing. Figure 50 shows the ESAI transmit timing diagram.
62 63 SCKT (Input/Output) 78 FST (bit) out 82 FST (word) out 83 79 64
86 84
86 87
first bit last bit
Data out 93 Transmitter #0 drive enable (internal signal)
89 91
85
88
FST (bit) in 92 90 FST (word) in 94 Flags out
Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period.
91
See Note
Figure 50. ESAI Transmit Timing
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor
Figure 51 shows the ESAI receive timing diagram.
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62 63 SCKR (input/output) 65 FSR (bit) out 69 FSR (word) out 72 71 Data in 73 FSR (bit) in 74 FSR (word) in 76 Flags in Figure 51. ESAI Receive Timing Diagram 77 75 75 first bit last bit 70 64 66
Figure 52 shows the ESAI HCKT timing diagram.
HCKT 95 96 Figure 52. ESAI HCKT Timing
SCKT (output)
i.MX25 Applications Processor for Automotive Products, Rev. 1 78 Freescale Semiconductor
Figure 53 shows the ESAI HCKR timing diagram.
HCKR 95 97 Figure 53. ESAI HCKR Timing
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SCKR (output)
Table 56 describes the general timing requirements for the ESAI module. Table 54 and Table 55 describe respectively the conditions and signals cited in Table 56.
Table 54. ESAI Timing Conditions
Symbol i ck x ck i ck a i ck s Significance Internal clock External clock Internal clock, asynchronous mode Internal clock, synchronous mode Comments In the i.MX25, the internal clock frequency is equal to the IP bus frequency (133 MHz) The external clock may be derived from the CRM module or other external clock sources In asynchronous mode, SCKT and SCKR are different clocks In synchronous mode, SCKT and SCKR are the same clock
Table 55. ESAI Signals
Signal Name SCKT SCKR FST HCKT HCKR Transmit clock Receive clock Transmit frame sync Transmit high-frequency clock Receive high-frequency clock Significance
Table 56. ESAI General Timing Requirements
No. 62 63 Clock cycle4 Clock high period For internal clock For external clock 64 Clock low period For internal clock For external clock Characteristics1 2 Symbol tSSICC -- -- -- -- -- Expression3 4 x Tc 4 x Tc -- 2 x Tc - 9.0 2 x Tc 2 x Tc - 9.0 2 x Tc Min. 30.0 30.0 -- 6 15 6 15 Max. -- -- -- -- -- -- -- -- Condition i ck i ck -- -- -- ns Unit ns ns
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 79
Table 56. ESAI General Timing Requirements (continued)
No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Characteristics1 2 SCKR rising edge to FSR out (bl) high SCKR rising edge to FSR out (bl) low SCKR rising edge to FSR out (wr) high5 SCKR rising edge to FSR out (wr) low 5 SCKR rising edge to FSR out (wl) high SCKR rising edge to FSR out (wl) low Data in setup time before SCKR (SCK in synchronous mode) falling edge Data in hold time after SCKR falling edge FSR input (bl, wr) high before SCKR falling edge5 FSR input (wl) high before SCKR falling edge FSR input hold time after SCKR falling edge Flags input setup before SCKR falling edge Flags input hold time after SCKR falling edge SCKT rising edge to FST out (bl) high SCKT rising edge to FST out (bl) low SCKT rising edge to FST out (wr) high5 SCKT rising edge to FST out (wr) low5 SCKT rising edge to FST out (wl) high SCKT rising edge to FST out (wl) low SCKT rising edge to data out enable from high impedance SCKT rising edge to transmitter #0 drive enable assertion Symbol -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Expression3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. -- -- -- -- -- -- -- -- -- -- -- -- 12.0 19.0 3.5 9.0 2.0 12.0 2.0 12.0 2.5 8.5 0.0 19.0 6.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 17.0 7.0 17.0 7.0 19.0 9.0 19.0 9.0 16.0 6.0 17.0 7.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18.0 8.0 20.0 10.0 20.0 10.0 22.0 12.0 19.0 9.0 20.0 10.0 22.0 17.0 17.0 11.0 Condition x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 56. ESAI General Timing Requirements (continued)
No. 86 87 88 89 90 91 92 93 94 95 96 97
1 2 3 4 5
Characteristics1 2 SCKT rising edge to data out valid SCKT rising edge to data out high impedance6 SCKT rising edge to transmitter #0 drive enable negation6 FST input (bl, wr) setup time before SCKT falling edge5 FST input (wl) setup time before SCKT falling edge FST input hold time after SCKT falling edge FST input (wl) to data out enable from high impedance FST input (wl) to transmitter #0 drive enable assertion Flag output valid after SCKT rising edge HCKR/HCKT clock cycle HCKT input rising edge to SCKT output HCKR input rising edge to SCKR output
Symbol -- -- -- -- -- -- -- -- -- -- -- --
Expression3 -- -- -- -- -- -- -- -- -- 2 x TC -- --
Min. -- -- -- -- -- -- 2.0 18.0 2.0 18.0 4.0 5.0 -- -- -- -- 15 -- --
Max. 18.0 13.0 21.0 16.0 14.0 9.0 -- -- -- -- -- -- 21.0 14.0 14.0 9.0 -- 18.0 18.0
Condition x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck -- -- x ck i ck -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
6
VCORE_VDD = 1.00 0.10 V; TJ = -40 C to 125 C, CL = 50 pF In the "Characteristics" column, bl = bit length, wl = word length, wr = word length relative In the "Expression" column, TC = 7.5 ns. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signal), until the second-to-last bit-clock of the first word in the frame. Periodically sampled and not 100% tested.
3.6.8
Enhanced Secured Digital Host Controller (eSDHCv2) Timing
Figure 54 shows eSDHCv2 timing, and Table 57 describes the timing parameters (SD1-SD8) used in the figure. The following definitions apply to values and signals described in Table 57: * LS: low-speed mode. Low-speed card can tolerate clocks up to 400 kHz * FS: full-speed mode. Full-speed MMC card's clock can reach 20 MHz; full speed SD/SDIO card clock can reach 25 MHz * HS: high-speed mode. High-speed MMC card's clock can reach 52 MHz; SD/SDIO card clock can reach 50 MHz
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SD4 SD1
SD5
CLK SD3 CMD DAT0 DAT1 ...... DAT7 CMD DAT0 DAT1 ...... DAT3 SD6
output from eSDHCv2 to card
SD7
SD8
input from card to eSDHCv2
Figure 54. eSDHCv2 Timing Table 57. eSDHCv2 Interface Timing Specification
ID Card Input Clock SD1 Clock frequency (low speed) Clock frequency (SD/SDIO full speed/high speed) Clock frequency (MMC full speed/high speed) Clock frequency (identification mode) SD2 SD3 SD4 SD5 Clock low time Clock high time Clock rise time Clock fall time fPP1 fPP2 fPP3 fOD tWL tWH tTLH tTHL 0 0 0 100 6.5 6.5 -- -- 400 25/50 20/52 400 -- -- 3 3 kHz MHz MHz kHz ns ns ns ns Parameter Symbols Min. Max. Unit
eSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 eSDHC output delay tOD -3 3 ns
eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD7 SD8
1 2
eSDHC input setup time eSDHC input hold time
tISU tIH
4
2.5 2.5
-- --
ns ns
In low-speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal-speed mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In high speed mode, clock frequency can be any value between 0 ~ 50 MHz. 3 In normal-speed mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In high speed mode, clock frequency can be any value between 0 ~ 52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
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SD2
3.6.9
Fast Ethernet Controller (FEC) Timing
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The FEC is designed to support both 10- and 100-Mbps Ethernet networks compliant with the IEEE 802.3 standard. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports 10/100 Mbps MII (18 pins altogether), 10/100 Mbps RMII (ten pins, including serial management interface) and the 10-Mbps-only 7-Wire interface (which uses seven of the MII pins), for connection to an external Ethernet transceiver. All signals are compatible with transceivers operating at a voltage of 3.3 V. The following subsections describe the timing for MII and RMII modes.
3.6.9.1
FEC MII Mode Timing
The following subsections describe MII receive, transmit, asynchronous inputs, and serial management signal timings. 3.6.9.1.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK)
The receiver functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the FEC_RX_CLK frequency. Figure 55 shows MII receive signal timings. Table 58 describes the timing parameters (M1-M4) shown in the figure.
M3 FEC_RX_CLK (input)
M4 FEC_RXD[3:0] (inputs) FEC_RX_DV FEC_RX_ER M1 M2
Figure 55. MII Receive Signal Timing Diagram Table 58. MII Receive Signal Timing
ID M1 M2 M3 M4 Characteristic1 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold FEC_RX_CLK pulse width high FEC_RX_CLK pulse width low Min. 5 5 35% 35% Max. -- -- 65% 65% Unit ns ns FEC_RX_CLK period FEC_RX_CLK period
1 FEC_RX_DV,
FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 83
3.6.9.1.2
MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and FEC_TX_CLK)
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The transmitter functions correctly up to an FEC_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the FEC_TX_CLK frequency. Figure 56 shows MII transmit signal timings. Table 59 describes the timing parameters (M5-M8) shown in the figure.
M7 FEC_TX_CLK (input) M5 M8 FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER M6 Figure 56. MII Transmit Signal Timing Diagram Table 59. MII Transmit Signal Timing
ID M5 M6 M7 M8 Characteristic1 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid FEC_TX_CLK pulse width high FEC_TX_CLK pulse width low Min. 5 -- 35% 35% Max. -- 20 65% 65% Unit ns ns FEC_TX_CLK period FEC_TX_CLK period
1 FEC_TX_EN,
FEC_TX_CLK, and FEC_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
3.6.9.1.3
MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)
Figure 57 shows MII asynchronous input timings. Table 60 describes the timing parameter (M9) shown in the figure.
FEC_CRS, FEC_COL M9 Figure 57. MII Async Inputs Timing Diagram
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Table 60. MII Asynchronous Inputs Signal Timing
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ID M91
1
Characteristic FEC_CRS to FEC_COL minimum pulse width
Min. 1.5
Max. --
Unit FEC_TX_CLK period
FEC_COL has the same timing in 10-Mbit 7-wire interface mode.
3.6.9.2
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3 standard MII specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz. Figure 58 shows MII asynchronous input timings. Table 61 describes the timing parameters (M10--M15) shown in the figure.
M14 M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12 M13
Figure 58. MII Serial Management Channel Timing Diagram Table 61. MII Serial Management Channel Timing
ID M10 M11 M12 M13 M14 M15 Characteristic FEC_MDC falling edge to FEC_MDIO output invalid (min. propagation delay) FEC_MDC falling edge to FEC_MDIO output valid (max. propagation delay) FEC_MDIO (input) to FEC_MDC rising edge setup FEC_MDIO (input) to FEC_MDC rising edge hold FEC_MDC pulse width high FEC_MDC pulse width low Min. 0 -- 18 0 40% 40% Max. -- 5 -- -- 60% 60% Unit ns ns ns ns FEC_MDC period FEC_MDC period
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 85
3.6.9.3
RMII Mode Timing
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In RMII mode, FEC_TX_CLK is used as the REF_CLK, which is a 50 MHz 50 ppm continuous reference clock. FEC_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and FEC_RX_ER. Figure 59 shows RMII mode timings. Table 62 describes the timing parameters (M16-M21) shown in the figure.
M16 M17
REF_CLK (input)
M18
FEC_TXD[1:0] (output) FEC_TX_EN
M19
CRS_DV (input) FEC_RXD[1:0] FEC_RX_ER
M20 M21
Figure 59. RMII Mode Signal Timing Diagram Table 62. RMII Signal Timing
ID M16 M17 M18 M19 M20 M21 Characteristic REF_CLK(FEC_TX_CLK) pulse width high REF_CLK(FEC_TX_CLK) pulse width low REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold Min. 35% 35% 3 -- 2 2 Max. 65% 65% -- 12 -- -- Unit REF_CLK period REF_CLK period ns ns ns ns
i.MX25 Applications Processor for Automotive Products, Rev. 1 86 Freescale Semiconductor
3.6.10
Controller Area Network (FlexCAN) Transceiver Parameters and Timing
Table 63. Tx Pin Characteristics
Parameter High-level output voltage Low-level output voltage
1
Table 63 and Table 64 show voltage requirements for the FlexCAN transceiver Tx and Rx pins.
Symbol
VOH VOL
Min. 2 --
Typ. -- 0.8
Max. Vcc1 + 0.3 --
Units V V
Vcc = +3.3 V 5%
Table 64. Rx Pin Characteristics
Parameter High-level input voltage Low-level input voltage
1
Symbol
VIH VIL
Min. 0.8 x Vcc1 --
Typ. -- 0.4
Max. Vcc1 --
Units V V
Vcc = +3.3 V 5%
Figure 60 through Figure 63 show the FlexCAN timing, including timing of the standby and shutdown signals.
TXD
VCC/2
VCC/2 tOFFTXD 0.9V
tONTXD VDIFF tONRXD RXD VCC/2
0.5V tOFFRXD VCC/2
Figure 60. FlexCAN Timing Diagram
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VCC x 0.75 Bus Externally Driven 1.1V VDIFF tSBRXDL tDRXDL RXD VCC/2 VCC/2
Figure 61. Timing Diagram for FlexCAN Standby Signal
SHDN
VCC/2 tOFFSHDN
VCC/2 tONSHDN
VDIFF
0.5V
Bus Externally Driven
RXD
VCC/2
Figure 62. Timing Diagram for FlexCAN Shutdown Signal
SHDN tSHDNSB
VCC/2
0.75 x V CC RS
Figure 63. Timing Diagram for FlexCAN Shutdown-to-Standby Signal
Because integer multiples are not possible, taking into account the range of frequencies at which the SoC has to operate, DPLLs work in FOL mode only.
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RS
3.6.11
Inter IC Communication (I2C) Timing
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
The I2C communication protocol consists of the following seven elements: * Start * Data source/recipient * Data direction * Slave acknowledge * Data * Data acknowledge * Stop Figure 64 shows the timing of the I2C module. Table 65 and Table 66 describe the I2C module timing parameters (IC1-IC6) shown in the figure.
I2DAT IC10 IC11 IC9
I2CLK
IC2
IC8
IC4
IC7
IC3
START
IC10 IC6 IC1 IC5
IC11
START
STOP
START
Figure 64. I2C Module Timing Diagram Table 65. I2C Module Timing Parameters: 3.0 V +/-0.30 V
Standard Mode ID IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12
1
Fast Mode Unit Min. 2.5 0.6 0.6 0.92 4
Parameter Min. I2CLK cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2CLK Clock LOW Period of the I2CLK Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both I2DAT and I2CLK signals Fall time of both I2DAT and I2CLK signals Capacitive load for each bus line (Cb) 10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 Max. 3.45 1000 300 400
2
Max. s s s s s s s ns s ns ns pF
01 0.6 1.3 0.6 100
3
1.3 20+0.1Cb
300 300 400
20+0.1Cb4 -
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 89
2 3
Table 66. I2C Module Timing Parameters: 1.8 V +/- 0.10 V
Standard Mode ID IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12
1
Parameter Min. I2CLK cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2CLK Clock LOW Period of the I2CLK Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both I2DAT and I2CLK signals Fall time of both I2DAT and I2CLK signals Capacitive load for each bus line (Cb) 10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 Max. 3.452 1000 300 400
Unit s s s s s s s ns s ns ns pF
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal
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The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time(ID No IC9) + data_setup_time(ID No IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF.
3.6.12
Liquid Crystal Display Controller (LCDC) Timing
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Figure 65 and Figure 66 show LCDC timing in non-TFT and TFT mode respectively, and Table 67 and Table 68 list the timing parameters used in the associated figures.
T5 VSYNC
HSYNC
Line 1
Line 2
Line n
Line 1
T2 HSYNC T1 LSCLK T3 LD T4 T6
Figure 65. LCDC Non-TFT Mode Timing Diagram Table 67. LCDC Non-TFT Mode Timing Parameters
ID T1 T2 T3 T4 T5 T6
1
Description Pixel clock period HSYNC width LD setup time LD hold time Wait between HSYNC and VSYNC rising edge Wait between last data and HSYNC rising edge
Min. 22.5 1 5 5 2 1
Max. 1000 -- -- -- -- --
Unit ns T1 ns ns T1 T1
T is pixel clock period
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 91
VSYNC
HSYNC
Line 1
Line 2
Line n
Line 1
HSYNC T2 T5 T6
OE T1 LSCLK T3 LD T4
Figure 66. LCDC TFT Mode Timing Diagram Table 68. LCDC TFT Mode Timing Parameters
ID T1 T2 T3 T4 T5 T6
1
Description Pixel clock period HSYNC width LD setup time LD hold time Delay from the end of HSYNC to the beginning of the OE pulse Delay from end of OE to the beginning of the HSYNC pulse
Min. 22.5 1 5 5 3 1
Ma 1000 -- -- -- -- --
Unit ns T1 ns ns T1 T1
T is pixel clock period
3.6.13
Pulse Width Modulator (PWM) Timing Parameters
Figure 67 depicts the timing of the PWM, and Table 69 lists the PWM timing characteristics. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse width modulator output (PWMO) external pin.
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2a PWM Source Clock 2b 3a 4a PWM Output
1 3b
4b
Figure 67. PWM Timing Table 69. PWM Output Timing Parameter
Ref No. 1 2a 2b 3a 3b 4a 4b
1
Parameter System CLK frequency1 Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time
Minimum 0 12.29 9.91 -- -- -- 8.71
Maximum ipg_clk -- -- 0.5 0.5 9.37 --
Unit MHz ns ns ns ns ns ns
CL of PWMO = 30 pF
3.6.14
Subscriber Identity Module (SIM) Timing
Each SIM module interface consists of a total of 12 pins (two separate ports, each containing six signals). Typically a port uses five signals. The interface is designed to be used with synchronous SIM cards, meaning the SIM module provides the clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard UART data exchanges. All six signals (five for bidirectional Tx/Rx) of the SIM module are asynchronous with each other. There are no required timing relationships between signals in normal mode. The SIM card is initiated by the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed information see ISO/IEC 7816).
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1/SI1
SIMx_CLKy
SI3 SI2
SIMx_DATAy_TX_RX SIMx_SIMPDy
SI4 SI4
SIMx_DATAy_TX_RX
SI5
SI5
SIMx_RSTy
SI6
SI6
Figure 68. SIM Clock Timing Diagram
Table 70 defines the general timing requirements for the SIM interface.
Table 70. Timing Specifications, High Drive Strength
ID SI1 SI2 SI3 SI4 SI5 SI6
1 2
Parameter SIM clock frequency (SIMx_CLKy)1 SIM clock rise time (SIMx_CLKy) SIM clock fall time (SIMx_CLKy)
2
Symbol Sfreq Srise Sfall Strans Tr/Tf Tr/Tf
4
Min. 0.01 -- -- 10 -- --
Max. 25 0.09 x (1/Sfreq) 0.09 x (1/Sfreq) 25 1 1
Unit MHz ns ns ns us us
3
SIM input transition time (SIMx_DATAy_RX_TX, SIMx_SIMPDy) SIM I/O rise time / fall time (SIMx_DATAy_RX_TX) SIM RST rise time / fall time (SIMx_RSTy)
5
50% duty cycle clock, With C = 50 pF 3 With C = 50 pF 4 With Cin = 30 pF, Cout = 30 pF, 5 With Cin = 30 pF,
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3.6.14.1
SIM Reset Sequences
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SIM cards may have internal reset, or active low reset. The following subset describes the reset sequences in these two cases. 3.6.14.1.1 SIM Cards with Internal Reset
Figure 69 shows the reset sequence for SIM cards with internal reset. The reset sequence comprises the following steps: * After power-up, the clock signal is enabled on SIMx_CLKy (time T0) * After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted. * The card must send a response on SIMx_DATAy_RX_TX acknowledging the reset between 400-40000 clock cycles after T0.
SIMn_SVENm
SIMx_CLKy
SIMx_DATAy_RX_TX
RESPONSE 1 2 T0 Figure 69. Internal Reset Card Reset Sequence
Table 71 defines the general timing requirements for the SIM interface.
Table 71. Timing Specifications, Internal Reset Card Reset Sequence
Ref No. 1 2 Min. -- 400 Max. 200 40,000 Units clk cycles clk cycles
3.6.14.1.2
SIM Cards with Active Low Reset
Figure 70 shows the reset sequence for SIM cards with active low reset. The reset sequence comprises the following steps: * After power-up, the clock signal is enabled on SIMx_CLKy (time T0) * After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted. * SIMx_RSTy must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those 40,000 clock cycles) * SIMx_RSTy is asserted (at time T1) * SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 95
SIMx_SVENy
SIMx_RSTy
SIMx_CLKy
SIMx_DATAy_RX_TX
RESPONSE 1 3 2 3 T1 Figure 70. Active-Low-Reset SIM Card Reset Sequence
T0
Table 72 defines the general timing requirements for the SIM interface.
Table 72. Timing Specifications, Active-Low-Reset SIM Card Reset Sequence
Ref No. 1 2 3 Min. -- 400 40,000 Max. 200 40,000 -- Unit clk cycles clk cycles clk cycles
3.6.14.2
SIM Power-Down Sequence
Figure 71 shows the SIM interface power-down AC timing diagram. Table 73 shows the timing requirements for parameters (SI7-SI10) shown in the figure. The power-down sequence for the SIM interface is as follows: * SIMx_SIMPDy port detects the removal of the SIM Card * SIMx_RSTy is negated * SIMx_CLKy is negated * SIMx_DATAy_RX_TX is negated * SIMx_SVENy is negated Each of the above steps requires one CKIL period (usually 32 kHz). Power-down may be initiated by a SIM card removal detection; or it may be launched by the processor.
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SI10
SIMx_RSTy
SI7
SIMx_CLKy
SI8
SIMx_RXy & SIMx_TXy
SI9
SIMx_VENy
Figure 71. SmartCard Interface Power Down AC Timing Table 73. Timing Requirements for Power-down Sequence
ID SI7 SI8 SI9 SI10 PARAMETER SIM reset to SIM clock stop SIM reset to SIM Tx data low SIM reset to SIM voltage enable low SIM presence detect to SIM reset low SYMBOL Srst2clk Srst2dat Srst2ven Spd2rst Min. 0.9 x 1/Fckil 1.8 x 1/Fckil 2.7 x 1/Fckil 0.9 x 1/Fckil Max. 1.1 x 1/Fckil 2.2 x 1/Fckil 3.3 x 1/Fckil 1.1 x 1/Fckil Unit ns ns ns ns
3.6.15
System JTAG Controller (SJC) Timing
Figure 72 through Figure 75 show respectively the test clock input, boundary scan, test access port, and TRST timings for the SJC. Table 74 describes the SJC timing parameters (SJ1-SJ13) indicated in the figures.
SJ1 SJ2 TCK (Input) VIH VIL SJ3 SJ3 VM SJ2 VM
Figure 72. Test Clock Input Timing Diagram
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SIMx_SIMPDy
TCK (Input) VIL SJ4 Data Inputs SJ6 Data Outputs SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Output Data Valid Input Data Valid
VIH
SJ5
Figure 73. Boundary Scan (JTAG) Timing Diagram
TCK (Input) VIL SJ8 TDI TMS (Input) SJ10 TDO (Output) SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Output Data Valid Input Data Valid SJ9
VIH
Figure 74. Test Access Port Timing Diagram
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SJ13 TRST (Input)
SJ12
Figure 75. TRST Timing Diagram Table 74. SJC Timing Parameters
All Frequencies ID SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8 SJ9 SJ10 SJ11 SJ12 SJ13
1
Parameter Min. TCK cycle time TCK clock pulse width measured at TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low
VM2
Unit Max. -- -- 3 -- -- 50 50 -- -- 44 44 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns 1001 40 -- 10 50 -- -- 10 50 -- -- 100 40
In cases where SDMA TAP is put in the chain, the maximum TCK frequency is limited by the maximum ratio of 1:8 of SDMA core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock. 2V M - mid point voltage
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TCK (Input)
3.6.16
Smart Liquid Crystal Display Controller (SLCDC)
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Figure 76 and Figure 77 show SLCDC timing for serial and parallel transfers respectively. Table 75 and Table 76 describe the timing parameters shown in the respective figures.
tcss LCD_CS LCD_CLK (LCD_DATA[6]) tds SDATA (LCD_DATA[7]) MSB trss RS RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 1, CSPOL = 0) tdh trsh LSB tcyc tcl tch tcsh
tcss LCD_CS LCD_CLK (LCD_DATA[6]) tds SDATA (LCD_DATA[7]) MSB trss RS tdh tcyc tcl tch
tcsh
trsh LSB
RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 0, CSPOL = 0) tcss tcsh tcyc tcl tch trsh LSB trss RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 1, CSPOL = 1) tcss tcsh tcyc tcl tch
LCD_CS LCD_CLK (LCD_DATA[6])
tds SDATA (LCD_DATA[7]) MSB
tdh
RS
LCD_CS LCD_CLK (LCD_DATA[6])
tds SDATA (LCD_DATA[7]) MSB trss RS
tdh
trsh LSB
RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 0, CSPOL = 1)
Figure 76. SLCDC Timing Diagram--Serial Transfers to LCD Device
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Table 75. SLCDC Serial Interface Timing Parameters
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Symbol tcss tcsh tcyc tcl tch tds tdh trss trsh Parameter Chip select setup time Chip select hold time Serial clock cycle time Serial clock low pulse Serial clock high pulse Data setup time Data hold time Register select setup time Register select hold time Min. (tcyc / 2) () tprop (tcyc / 2) () tprop 39 () tprop 18 () tprop 18 () tprop (tcyc / 2) () tprop (tcyc / 2) () tprop (15 x tcyc / 2) () tprop (tcyc / 2) () tprop Typ. -- -- -- -- -- -- -- -- -- Max. -- -- 2641 -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns
LCD_CLK trss LCD_RS tcyc LCD_CS tds LCD_DATA[15:0] tdh display data trsh
command data
(This diagram shows the case CSPOL=0)
LCD_CLK trss LCD_RS tcyc LCD_CS tds LCD_DATA[15:0] tdh display data trsh
command data
(This diagram shows the case CSPOL=1)
Figure 77. SLCDC Timing Diagram--Parallel Transfers to LCD Device
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Table 76. SLCDC Parallel Interface Timing Parameters
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Symbol tcyc tds tdh trss trsh Parameter Parallel clock cycle time Data setup time Data hold time Register select setup time Register select hold time 78 () tprop (tcyc / 2) () tprop (tcyc / 2) () tprop (tcyc / 2) () tprop (tcyc / 2) () tprop Min. Typ. -- -- -- -- -- Max. 4923 -- -- -- -- Units ns -- -- -- --
3.6.17
Synchronous Serial Interface (SSI) Timing
The following subsections describe SSI timing in four cases: * Transmitter with external clock * Receiver with external clock * Transmitter with internal clock * Receiver with internal clock
3.6.17.1
SSI Transmitter Timing with Internal Clock
Figure 78 shows the timing for SSI transmitter with internal clock, and Table 77 describes the timing parameters (SS1-SS52).
SS1 SS2 AUDn_TXC (Output) SS6 AUDn_TXFS (bl) (Output) SS10 AUDn_TXFS (wl) (Output) SS16 AUDn_TXD (Output) SS43 SS42 AUDn_RXD (Input) Note: SRXD Input in Synchronous mode only SS19 SS14 SS15 SS17 SS18 SS12 SS8 SS5 SS4 SS3
Figure 78. SSI Transmitter with Internal Clock Timing Diagram
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Table 77. SSI Transmitter Timing with Internal Clock
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ID Parameter Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS6 SS8 SS10 SS12 SS14 SS15 SS16 SS17 SS18 SS19 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx/Rx) internal FS rise time (Tx/Rx) internal FS fall time (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance STXD rise/fall time Synchronous Internal Clock Operation SS42 SS43 SS52 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling Loading 10.0 0.0 -- -- -- 25.0 ns ns pf 81.4 36.0 -- 36.0 -- -- -- -- -- -- -- -- -- -- -- -- -- 6.0 -- 6.0 15.0 15.0 15.0 15.0 6.0 6.0 15.0 15.0 15.0 6.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit
Note: * All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. * All timings are on pads when SSI is being used for a data transfer. * "Tx" and "Rx" refer, respectively, to the transmit and receive sections of the SSI. * For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation).
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3.6.17.2
SSI Receiver Timing with Internal Clock
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Figure 79 shows the timing for the SSI receiver with internal clock. Table 78 describes the timing parameters (SS1-SS51) shown in the figure.
SS1 SS5 SS2 AUDn_TXC (Output) SS7 AUDn_TXFS (bl) (Output) AUDn_TXFS (wl) (Output) SS20 SS21 AUDn_RXD (Input) SS47 SS48 AUDn_RXC (Output) SS51 SS50 SS49 SS9 SS4 SS3
SS11
SS13
Figure 79. SSI Receiver Internal Clock Timing Diagram Table 78. SSI Receiver Timing with Internal Clock
ID Parameter Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS7 SS9 SS11 SS13 SS20 SS21 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low Oversampling Clock Operation SS47 Oversampling clock period 15.04 -- ns 81.4 36.0 -- 36.0 -- -- -- -- -- 10.0 0.0 -- -- 6.0 -- 6.0 15.0 15.0 15.0 15.0 -- -- ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit
i.MX25 Applications Processor for Automotive Products, Rev. 1 104 Freescale Semiconductor
Table 78. SSI Receiver Timing with Internal Clock (continued)
ID SS48 SS49 SS50 SS51 Parameter Oversampling clock high period Oversampling clock rise time Oversampling clock low period Oversampling clock fall time Min. 6.0 -- 6.0 -- Max. -- 3.0 -- 3.0 Unit ns ns ns ns
Note: * All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. * All timings are on pads when SSI is being used for a data transfer. * "Tx" and "Rx" refer to the transmit and receive sections of the SSI. * For internal frame sync operation using external clock, the FS timing is the same as that of Tx Data (for example, during AC97 mode of operation).
3.6.17.3
SSI Transmitter Timing with External Clock
Figure 80 shows the timing for the SSI transmitter with external clock. Table 79 describes the timing parameters (SS22-SS46) shown in the figure.
SS22 SS23 SS25 SS26 SS24
AUDn_TXC (Input) SS27 AUDn_TXFS (bl) (Input) SS31 AUDn_TXFS (wl) (Input) SS39 SS37 AUDn_TXD (Output) SS45 SS44 AUDn_RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS38 SS29
SS33
Figure 80. SSI Transmitter with External Clock Timing Diagram
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Table 79. SSI Transmitter Timing with External Clock
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
ID Parameter External Clock Operation SS22 SS23 SS24 SS25 SS26 SS27 SS29 SS31 SS33 SS37 SS38 SS39 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time FS (bl) low/ high setup before (Tx) CK falling FS (bl) low/ high setup before (Tx) CK falling FS (wl) low/ high setup before (Tx) CK falling FS (wl) low/ high setup before (Tx) CK falling (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance Synchronous External Clock Operation SS44 SS45 SS46 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling SRXD rise/fall time 10.0 2.0 -- -- -- 6.0 ns ns ns 81.4 36.0 -- 36.0 -- -10.0 10.0 -10.0 10.0 -- -- -- -- -- 6.0 -- 6.0 15.0 -- 15.0 -- 15.0 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit
Note: * All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables figures. * All timings are on pads when SSI is being used for data transfer. * "Tx" and "Rx" refer, respectively, to the transmit and receive sections of the SSI. * For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation).
i.MX25 Applications Processor for Automotive Products, Rev. 1 106 Freescale Semiconductor
3.6.17.4
SSI Receiver Timing with External Clock
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Figure 81 shows the timing for SSI receiver with external clock. Table 80 describes the timing parameters (SS22-SS41) used in the figure.
SS22 SS26 SS23 SS25 SS24
AUDn_TXC (Input) SS28 AUDn_TXFS (bl) (Input) SS32 AUDn_TXFS (wl) (Input) SS35 SS41 SS40 AUDn_RXD (Input) SS36 SS34 SS30
Figure 81. SSI Receiver with External Clock Timing Diagram Table 80. SSI Receiver Timing with External Clock
ID Parameter External Clock Operation SS22 SS23 SS24 SS25 SS26 SS28 SS30 SS32 SS34 SS35 SS36 SS40 SS41 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time FS (bl) low/high setup before (Tx) CK falling FS (bl) low/high setup before (Tx) CK falling FS (wl) low/high setup before (Tx) CK falling FS (wl) low/high setup before (Tx) CK falling (Tx/Rx) External FS rise time (Tx/Rx) External FS fall time SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 81.4 36.0 -- 36.0 -- -10.0 10.0 -10.0 10.0 -- -- 10.0 2.0 -- -- 6.0 -- 6.0 15.0 -- 15.0 -- 6.0 6.0 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit
Note: * All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. * All timings are on pads when SSI is being used for data transfer.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 107
* "Tx" and "Rx" refer, respectively, to the transmit and receive sections of the SSI. * For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation).
3.6.18
Touchscreen ADC Electrical Specifications and Timing
This section describes the electrical specifications, operation modes, and timing of the touchscreen ADC.
3.6.18.1
ADC Electrical Specifications
Table 81. Touchscreen ADC Electrical Specifications
Table 81 shows the electrical specifications for the touchscreen ADC.
Parameter
Conditions ADC
Min.
Typ.
Max.
Unit
Input sampling capacitance (CS) Resolution
No pin/pad capacitance included -- Analog Bias
--
2 12
--
pF bits
Resistance value between ref and agndref
-- Timing Characteristics
--
1.6
--
k
Sampling rate (fs) Internal ADC/TSC clock frequency Multiplexed inputs Data latency Power-up time1 clk falling edge to sampling delay (tsd) soc input setup time before clk rising edge (tsocst) soc input hold time after clk rising edge (tsochld) eoc delay after clk rise edge (teoc) With a 250fF load
-- -- -- -- -- -- --
-- --
-- -- 8 12.5 14
125 1.75
kHz MHz -- clk cycles clk cycles
2 0.5
5 1
8 3
ns ns
--
2 2 5
3 7 8
6 10 13
ns ns ns
Valid data out delay after With a 250fF load eoc rise edge (tdata)
i.MX25 Applications Processor for Automotive Products, Rev. 1 108 Freescale Semiconductor
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Table 81. Touchscreen ADC Electrical Specifications (continued)
Parameter Conditions Power Supply Requirements Current consumption2 NVCC_ADC QVDD Power-down current NVCC_ADC QVDD -- -- -- 2.1 0.5 1 10 mA mA uA uA Min. Typ. Max. Unit
--
--
--
Touchscreen Interface Expected plate resistance Switch drivers on resistance GND and VDD switches Conversion Characteristics3 DNL4 INL4 Gain + Offset Error
1
--
100 --
-- --
1500 10

fin = 1 kHz fin = 1 kHz --
-- -- --
+/-0.75 +/-2.0 --
-- -- +/-2
LSB LSB %FS
This comprises only the required initial dummy conversion cycle. Additional power-up time depends on the enadc, reset and soc signals applied to the touchscreen controller. 2 This value only includes the ADC and the driver switches, but it does not take into account the current consumption in the touchscreen plate. For example, if the plate resistance is 100 W, the total current consumption is about 33 mA. 3 At avdd = 3.3 V, dvdd = 1.2 V, Tjunction = 50 C, fclk = 1.75 MHz, any process corner, unless otherwise noted. 4 Value measured with a -0.5 dBFS sinusoidal input signal and computed with the code density test.
3.6.18.2
ADC Timing Diagrams
Figure 82 represents the synchronization between the signals clk, soc, eoc, and the output bits in the usage of the internal ADC. After a conversion cycle eoc is asserted, a new conversion begins only when the assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 109
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Figure 82. Start-up Sequence
The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw, xnsw) are totally asynchronous. The following conditions are necessary to guarantee the correct operation of the ADC: * The input multiplexer selection (selin11...selin0) is stable during both the last clock cycle (14th) and the first clock cycle (1st). The best way to guarantee this is to make the input multiplexer selection during clock cycles 2 to 13. * The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it only after an eoc pulse has been acquired, during the last clock cycle (14).
i.MX25 Applications Processor for Automotive Products, Rev. 1 110 Freescale Semiconductor
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Figure 83 shows the timing for ADC normal operation.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Figure 83. Timing for ADC Normal Operation
When the ADC is used so that the idle clock cycles occur between conversions (due to the negation of soc), the selin inputs must be stable at least 1 clock cycle before the clock's rising edge where the soc signal is latched. Also, selrefp and selrefn must be stable by the time the soc signal is latched. These conditions are met if enadc=1 and reset=0 throughout ADC operation, including the idle cycles. If the conditions are not met, or if power is lost during ADC operation, then a new start-up sequence is required for ADC to become operational again.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 111
Figure 84 represents the usage of the ADC with idle cycles between conversions. This diagram is valid for any value of N equal or greater than 1.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Figure 84. ADC Usage with Idle Cycles Between Conversions
3.6.19
UART Timing
This section describes the timing of the UART module in serial and parallel mode.
3.6.19.1
3.6.19.1.1
UART RS-232 Serial Mode Timing
UART Transmit Timing in RS-232 Serial Mode
Figure 85 shows the UART transmit timing in RS-232 serial mode, showing only 8 data bits and 1 stop bit. Table 82 describes the timing parameter (UA1) shown in the figure.
UA1
Start Bit
UA1
Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT
TXD (output)
Bit 0
Bit 1
Bit 2
Bit 3
Next Start Bit
UA1
UA1
Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram
i.MX25 Applications Processor for Automotive Products, Rev. 1 112 Freescale Semiconductor
Table 82. UART RS-232 Serial Mode Transmit Timing Parameters
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
ID UA1
1 2
Parameter Transmit Bit Time
Symbol tTbit
Min. 1/Fbaud_rate1 - Tref_clk2
Max. 1/Fbaud_rate + Tref_clk
Units --
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
3.6.19.1.2
UART Receive Timing in RS-232 Serial Mode
Figure 86 shows the UART receive timing in RS-232 serial mode, showing only 8 data bits and 1 stop bit. Table 83 describes the timing parameter (UA2) shown in the figure.
-
UA2
Start Bit
UA2
Possible Parity Bit Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT Next Start Bit
RXD (input)
Bit 0
Bit 1
Bit 2
Bit 3
UA2
UA2
Figure 86. UART RS-232 Serial Mode Receive Timing Diagram Table 83. UART RS-232 Serial Mode Receive Timing Parameters
ID UA2
1
Parameter Receive bit time1
Symbol tRbit
Min.
Max.
Units --
1/Fbaud_rate2 - 1/(16 1/F baud_rate + 1/(16 x F baud_rate) x Fbaud_rate)
Note: The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16 x Fbaud_rate). 2F baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
3.6.19.2
UART Infrared (IrDA) Mode Timing
The following subsections describe the UART transmit and receive timing in IrDA mode. 3.6.19.2.3 UART IrDA Mode Transmit Timing
Figure 87 depicts the UART transmit timing in IrDA mode, showing only 8 data bits and 1 stop bit. Table 84 describes the timing parameters (UA3-UA4) shown in the figure.
UA3 UA3 UA4 UA3 UA3
TXD (output) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT
Figure 87. UART IrDA Mode Transmit Timing Diagram
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 113
Table 84. UART IrDA Mode Transmit Timing Parameters
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
ID UA3 UA4
1 2
Parameter Transmit bit time in IrDA mode Transmit IR pulse duration
Symbol tTIRbit tTIRpulse
Min. 1/Fbaud_rate1 - Tref_clk2
Max. 1/Fbaud_rate + Tref_clk
Units -- --
(3/16) x (1/Fbaud_rate) - Tref_clk (3/16) x (1/Fbaud_rate) + Tref_clk
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
3.6.19.2.4
UART IrDA Mode Receive Timing
Figure 88 shows the UART receive timing for IrDA mode, for a format of 8 data bits and 1 stop bit. Table 85 describes the timing parameters (UA5-UA6) shown in the figure.
UA5 UA5 UA6 UA5 UA5
RXD (input) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Possible Parity Bit STOP BIT
Figure 88. UART IrDA Mode Receive Timing Diagram Table 85. UART IrDA Mode Receive Timing Parameters
ID UA5 UA6
1
Parameter Receive bit time1 in IrDA mode Receive IR pulse duration
Symbol tRIRbit tRIRpulse
Min. 1/Fbaud_rate2 - 1/(16 x Fbaud_rate) 1.41 us
Max. 1/Fbaud_rate + 1/(16 x F baud_rate) (5/16) x (1/Fbaud_rate)
Units -- --
Note: The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16 x Fbaud_rate). 2F baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
3.6.20
USBOTG Timing
This section describes timing for the USB OTG port and host ports. Both serial and parallel interfaces are described.
3.6.20.1
USB Serial Interface Timing
The USB serial transceiver is configurable to four modes supporting four different serial interfaces: * DAT_SE0 bidirectional, 3-wire mode * DAT_SE0 unidirectional, 6-wire mode * VP_VM bidirectional, 4-wire mode * VP_VM unidirectional, 6-wire mode The following subsections describe the timings for these four modes.
i.MX25 Applications Processor for Automotive Products, Rev. 1 114 Freescale Semiconductor
3.6.20.1.1
DAT_SE0 Bidirectional Mode Timing
Table 86. Signal Definitions--DAT_SE0 Bidirectional Mode
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115
Table 86 defines the DAT_SE0 bidirectional mode signals.
Name USB_TXOE_B USB_DAT_VP USB_SE0_VM
Direction Out Out In Out In Transmit enable, active low
Signal Description
Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 Rx indicator when USB_TXOE_B is high
Figure 89 shows the USB transmit waveform in DAT_SE0 bidirectional mode diagram. Transmit USB_DAT_VP USB_SE0_VM US4 US1 US2
Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode
Figure 90 shows the USB receive waveform in DAT_SE0 bidirectional mode diagram. Receive
USB_TXOE_B USB_DAT_VP USB_SE0_VM
US5
US7/US8
US6
Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor
Table 87 shows the OTG port timing specification in DAT_SE0 bidirectional mode.
Table 87. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode
No. US1 US2 US3 US4 US5 US6 US7 US8 Parameter Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Enable Delay Disable Delay Rx rise/fall time Rx rise/fall time Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_SE0_VM Direction Out Out Out Out In In In In Min. -- -- -- 49.0 -- -- -- -- Max. 5.0 5.0 5.0 51.0 8.0 10.0 3.0 3.0 Unit ns ns ns % ns ns ns ns Conditions/ Reference Signal 50 pF 50 pF 50 pF -- USB_TXOE_B USB_TXOE_B 35 pF 35 pF
3.6.20.1.2
DAT_SE0 Unidirectional Mode Timing
Table 88. Signal Definitions--DAT_SE0 Unidirectional Mode
Table 88 defines the DAT_SE0 unidirectional mode signals.
Name USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV Direction Out Out Out In In In Signal Description Transmit enable, active low Tx data when USB_TXOE_B is low SE0 drive when USB_TXOE_B is low Buffered data on DP when USB_TXOE_B is high Buffered data on DM when USB_TXOE_B is high Differential Rx data when USB_TXOE_B is high
Figure 91 shows the USB transmit waveform in DAT_SE0 unidirectional mode diagram. Transmit
USB_DAT_VP
USB_SE0_VM
US9 US12
Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode
US10
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Figure 92 shows the USB receive waveform in DAT_SE0 unidirectional mode diagram.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Receive
USB_DAT_VP USB_SE0_VM RCV
US13
US17
US14
Figure 92. USB Receive Waveform in DAT_SE0 Unidirectional Mode
Table 89 shows the USB port timing specification in DAT_SE0 unidirectional mode.
Table 89. USB Port Timing Specification in DAT_SE0 Unidirectional Mode
No. US9 US10 US11 US12 US13 US14 US15 US16 US17 Parameter Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Enable Delay Disable Delay Rx rise/fall time Rx rise/fall time Rx rise/fall time Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV Signal Source Out Out Out Out In In In In In Min. -- -- -- 49.0 -- -- -- -- -- Max. 5.0 5.0 5.0 51.0 8.0 10.0 3.0 3.0 3.0 Unit ns ns ns % ns ns ns ns ns Condition/ Reference Signal 50 pF 50 pF 50 pF -- USB_TXOE_B USB_TXOE_B 35 pF 35 pF 35 pF
3.6.20.1.3
VP_VM Bidirectional Mode Timing
Table 90. Signal Definitions--VP_VM Bidirectional Mode
Table 90 defines the VP_VM bidirectional mode signals.
Name USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_RCV
Direction Out Out (Tx) In (Rx) Out (Tx) In (Rx) In
Signal Description * Transmit enable, active low * Tx VP data when USB_TXOE_B is low * Rx VP data when USB_TXOE_B is high * Tx VM data when USB_TXOE_B low * Rx VM data when USB_TXOE_B high * Differential Rx data
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 117
Figure 93 shows the USB transmit waveform in VP_VM bidirectional mode diagram.
Transmit
USB_TXENB US4 US2
USB_VPOUT
USB_VMOUT US3
Figure 93. USB Transmit Waveform in VP_VM Bidirectional Mode
Figure 94 shows the USB receive waveform in VP_VM bidirectional mode diagram.
Receive US5
USB_VPIN
USB_VMIN US6
Figure 94. USB Receive Waveform in VP_VM Bidirectional Mode
Table 91 shows the USB port timing specification in VP_VM bidirectional mode.
Table 91. USB Port Timing Specifications in VP_VM Bidirectional Mode
No. US18 US19 US20 US21 US22 US23 US24 US25 Parameter Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Tx high overlap Tx low overlap Enable delay Disable delay Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_SE0_VM USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_SE0_VM Direction Out Out Out Out Out Out In In Min. -- -- -- 49.0 0.0 -- -- -- Max. 5.0 5.0 5.0 51.0 -- 0.0 8.0 10.0 Unit ns ns ns % ns ns ns ns Condition/ Reference Signal 50 pF 50 pF 50 pF -- USB_DAT_VP USB_DAT_VP USB_TXOE_B USB_TXOE_B
i.MX25 Applications Processor for Automotive Products, Rev. 1 118 Freescale Semiconductor
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US1
Table 91. USB Port Timing Specifications in VP_VM Bidirectional Mode (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
No. US26 US27 US28 US29 Parameter Rx rise/fall time Rx rise/fall time Rx skew Rx skew Signal Name USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_RCV Direction In In Out Out Min. -- -- -4.0 -6.0 Max. 3.0 3.0 +4.0 +2.0 Unit ns ns ns ns Condition/ Reference Signal 35 pF 35 pF USB_SE0_VM USB_DAT_VP
3.6.20.1.4
VP_VM Unidirectional Mode Timing
Table 92. Signal Definitions for USB VP_VM Unidirectional Mode
Table 92 defines the signals for USB in VP_VM unidirectional mode.
Name USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV Direction Out Out Out In In In Signal Description Transmit enable, active low Tx VP data when USB_TXOE_B is low Tx VM data when USB_TXOE_B is low Rx VP data when USB_TXOE_B is high Rx VM data when USB_TXOE_B is high Differential Rx data
Figure 95 shows the USB transmit waveform in VP_VM unidirectional mode diagram. Transmit US32
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US30 US33 US31
US34
Figure 95. USB Transmit Waveform in VP_VM Unidirectional Mode
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 119
Figure 96 shows the USB receive waveform in VP_VM unidirectional mode diagram.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Receive
USB_TXOE_B
USB_VP1
US36
USB_VM1
US38
US37
US40 US39
USB_RCV
US41
Figure 96. USB Receive Waveform in VP_VM Unidirectional Mode
Table 93 shows the timing specifications for USB in VP_VM unidirectional mode.
Table 93. USB Timing Specifications in VP_VM Unidirectional Mode
No. US30 US31 US32 US33 US34 US35 US36 US37 US38 US39 US40 US41 Parameter Tx rise/fall time Tx rise/fall time Tx rise/fall time Tx duty cycle Tx high overlap Tx low overlap Enable delay Disable delay Rx rise/fall time Rx rise/fall time Rx skew Rx skew Signal USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_SE0_VM USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_VP1 USB_RCV Direction Out Out Out Out Out Out In In In In Out Out Min. -- -- -- 49.0 0.0 -- -- -- -- -- -4.0 -6.0 Max. 5.0 5.0 5.0 51.0 -- 0.0 8.0 10.0 3.0 3.0 +4.0 +2.0 Unit ns ns ns % ns ns ns ns ns ns ns ns Conditions/ Reference Signal 50 pF 50 pF 50 pF -- USB_DAT_VP USB_DAT_VP USB_TXOE_B USB_TXOE_B 35 pF 35 pF USB_SE0_VM USB_DAT_VP
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3.6.20.2
USB Parallel Interface Timing
Table 94. Signal Definitions for USB Parallel Interface
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 94 defines the USB parallel interface signals.
Name USB_Clk USB_Data[7:0] USB_Dir USB_Stp USB_Nxt
Direction In I/O In Out In
Signal Description Interface clock--All interface signals are synchronous to USB_Clk Bidirectional data bus, driven low by the link during idle--Bus ownership is determined by the direction Direction--Control the direction of the data bus Stop--The link asserts this signal for oneclock cycle to stop the data stream currently on the bus Next--The PHY asserts this signal to throttle the data
Figure 97 shows the USB parallel mode transmit/receive waveform. Table 95 describes the timing parameters (USB15-USB17) shown in the figure.
USB_Clk
US15 USB_Stp US15 USB_Data
US16
US16
US17 USB_Dir/Nxt
US17
Figure 97. USB Parallel Mode Transmit/Receive Waveform Table 95. USB Timing Specification in Parallel Mode
ID US15 US16 US17 Parameter Setup time (Dir&Nxt in, Data in) Hold time (Dir&Nxt in, Data in) Output delay time (Stp out, Data out Min. -- -- -- Max. 6.0 0.0 9.0 Unit ns ns ns Conditions/ Reference Signal 10 pF 10 pF 10 pF
4
4.1
Package Information and Contact Assignment
400 MAPBGA--Case 17x17 mm, 0.8 mm Pitch
Figure 98 shows the i.MX25 production package. The following notes apply to Figure 98: * All dimensions in millimeters. * Dimensioning and tolerancing per ASME Y14.5M-1994.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 121
Figure 98.
zzxzi.M
X25 Production Package
4.2
Ground, Power, Sense, and Reference Contact Assignments
Table 96. Ground, Power Sense, and Reference Contact Assignments
Contact Name BATT_VDD FUSE_VDD MPLL_GND MPLL_VDD NGND_ADC NVCC_ADC NVCC_CRM P10 T17 U17 U18 Y13 W13 N14 Contact Assignment
Figure 96 shows ground, power, sense, and reference contact assignments.
i.MX25 Applications Processor for Automotive Products, Rev. 1 122 Freescale Semiconductor
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* * *
Maximum solder bump diameter measured parallel to datum A. Datum A, the seating plane, is determined by the spherical crowns of the solder bumps. Parallelism measurement shall exclude any effect of mark on top surface of package.
Table 96. Ground, Power Sense, and Reference Contact Assignments (continued)
Contact Name NVCC_CSI NVCC_DRYICE NVCC_EMI1 NVCC_EMI2 NVCC_JTAG NVCC_LCDC NVCC_MISC NVCC_NFC NVCC_SDIO OSC24M_GND OSC24M_VDD QGND J13, J14 W11 G6, G7, G8, G9, H6, H7, H8, J6, J7 G12, G13, G14, G15, H12, H13, H14 U10 P6, P7, R6, R7 N5, N6, N7 L6, L7, L8 R17 W15 W16 A1, A11, A20, B11, C11, D11, E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, E16, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, G5, G10, G16, H5, H9, H10, H11, H15, H16, J5, J9, J10, J11, J15, J16, K1, K2, K3, K4, K5, K8, K9, K10, K11, K13, K14, K15, L5, L9, L10, L11, L12, L13, L14, L15, M8, M9, M10, M11, M12, M13, M14, M15, N9, N12, N13, N15, N16, P5, P13, P14, P15, P16, R5, R8, R9, R10, R11, R12, R13, R14, R15, R16, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, Y1, Y20 G11, J8, J12, K6, K7, K12, M5, M6, M7, N8, P8, P9 V11 M16 L16 M17 N17 K16 K19 L19 J17 W18 W17 Contact Assignment
QVDD REF UPLL_GND UPLL_VDD USBPHY1_UPLLVDD USBPHY1_UPLLVSS USBPHY1_VDDA USBPHY1_VDDA_BIAS USBPHY1_VSSA USBPHY1_VSSA_BIAS USBPHY2_VDD USBPHY2_VSS
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 123
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4.3
Signal Contact Assignments--17x17mm, 0.8mm Pitch
Table 97. i.MX25 Signal Contact Assignment
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Table 97 lists the i.MX25 signal contact assignments.
Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 MA10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 SD0 SD1 SD2 SD3
Contact Assignment A18 B17 C17 B18 C20 A19 C19 B19 D18 C18 A2 D16 D20 D17 D19 A3 B4 C6 B5 D7 A4 B6 C7 A5 A6 B7 A7 A12 C13 B13 D14
Signal Name NFWE_B NFRE_B NFALE NFCLE NFWP_B NFRB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8
Contact Assignment G4 C1 F4 E4 H4 C2 J2 J1 H2 H3 F1 F2 D1 E2 J3 H1 G1 G2 G3 E1 F3 E3 Y7 V8 W7 U8 Y6 V7 W6 Y5 V6
Signal Name SD1_CMD SD1_CLK SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 KPP_ROW0 KPP_ROW1 KPP_ROW2 KPP_ROW3 KPP_COL0 KPP_COL1 KPP_COL2 KPP_COL3 FEC_MDC FEC_MDIO FEC_TDATA0 FEC_TDATA1 FEC_TX_EN FEC_RDATA0 FEC_RDATA1 FEC_RX_DV FEC_TX_CLK RTCK TCK TMS TDI TDO TRSTB DE_B SJC_MOD
Contact Assignment K20 M20 L20 N20 M19 J20 N4 R1 P3 P2 P1 N3 N2 N1 L1 L2 L3 J4 M2 M1 M4 M3 L4 W10 V10 Y9 W9 Y8 V9 W8 U9
i.MX25 Applications Processor for Automotive Products, Rev. 1 124 Freescale Semiconductor
Table 97. i.MX25 Signal Contact Assignment (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Signal Name SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SDBA1 SDBA0 DQM0 DQM1 RAS CAS SDWE SDCKE0 SDCKE1 SDCLK SDCLK_B SDQS0 SDQS1 EB0 EB1 OE CS0 CS1 CS2 CS3 CS4 CS5 Contact Assignment D13 A13 D12 A10 B9 D10 B10 C10 C9 A9 D9 A8 A16 B15 C12 C8 C14 C16 A15 D15 C15 B14 A14 B12 B8 B3 C5 D6 C3 D3 B16 A17 D5 D4 Signal Name LD9 LD10 LD11 LD12 LD13 LD14 LD15 HSYNC VSYNC LSCLK OE_ACD CONTRAST PWM CSI_D2 CSI_D3 CSI_D4 CSI_D5 CSI_D6 CSI_D7 CSI_D8 CSI_D9 CSI_MCLK CSI_VSYNC CSI_HSYNC CSI_PIXCLK I2C1_CLK I2C1_DAT CSPI1_MOSI CSPI1_MISO CSPI1_SS0 CSPI1_SS1 CSPI1_SCLK CSPI1_RDY UART1_RXD Contact Assignment W5 Y4 Y3 V5 W4 V4 W3 U7 U6 U5 V3 U4 W2 F18 E19 F19 G18 E20 E18 G19 F20 H18 G20 H19 H20 F17 G17 T4 W1 R4 V2 U3 V1 U2 Signal Name USBPHY1_VBUS USBPHY1_DP USBPHY1_DM USBPHY1_UID USBPHY1_RREF USBPHY2_DM USBPHY2_DP GPIO_A GPIO_B GPIO_C GPIO_D GPIO_E GPIO_F EXT_ARMCLK UPLL_BYPCLK VSTBY_REQ VSTBY_ACK POWER_FAIL RESET_B POR_B CLKO BOOT_MODE0 BOOT_MODE1 CLK_SEL TEST_MODE OSC24M_EXTAL OSC24M_XTAL OSC32K_EXTAL OSC32K_XTAL TAMPER_A TAMPER_B MESH_C MESH_D OSC_BYP Contact Assignment K17 L18 K18 J18 L17 Y19 Y18 N19 N18 P17 P19 P18 R19 R20 U20 R18 T20 T19 T18 U19 V20 V19 W20 W19 V18 Y15 Y16 Y11 Y10 N10 N11 P11 P12 Y12
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 125
Table 97. i.MX25 Signal Contact Assignment (continued)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX251AVM4 and MCIMX255AVM4.
Signal Name NF_CE0 ECB LBA BCLK RW Contact Assignment D2 B2 B1 D8 C4 Signal Name UART1_TXD UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS Contact Assignment U1 T3 T2 P4 T1 R3 R2 Signal Name XP XN YP YN WIPER INAUX0 INAUX1 INAUX2 Contact Assignment V14 U13 V13 W12 U14 U11 V12 U12
Table 98 lists the i.MX25 no connect contact assignments.
Table 98. i.MX25 No Connect Contact Assignments
Signal Name NC_BGA_B20 NC_BGA_E17 NC_BGA_H17 NC_BGA_J19 NC_BGA_M18 NC_BGA_P20 NC_BGA_U15 NC_BGA_U16 NC_BGA_V15 NC_BGA_V16 NC_BGA_V17 NC_BGA_W14 NC_BGA_Y2 NC_BGA_Y14 NC_BGA_Y17 B20 E17 H17 J19 M18 P20 U15 U16 V15 V16 V17 W14 Y2 Y14 Y17 Contact Assignment
i.MX25 Applications Processor for Automotive Products, Rev. 1 126 Freescale Semiconductor
20 QGND 19 A5 18 A0 17 CS3 16 SDBA1 15 SDWE 14 SDCLK_B SDCLK 13 SD5 SD2 SDQS0 QGND SD10 SD8 SDQS1 A24 A20 A17 A15 EB0 ECB 1 QGND A LBA B SD12 DQM1 A21 A16 EB1 RW CS0 NFRB SD11 SD9 SD14 BCLK A18 OE CS4 CS5 CS1 QGND QGND DQM0 SD6 QGND QGND QGND QGND QGND QGND QGND QGND NFCLE D0 NF_CE0 D8 NFRE_B D9 C D D2 E SD1 SD4 QGND RAS SD3 QGND SDBA0 SDCKE1 SDCKE0 QGND QGND QGND QGND QGND QGND QGND QGND QGND QGND QGND QGND NFALE D1 D10 D11 F CS2 CAS MA10 QGND QGND A1 A2 A12 A3 A9 A8 CSI_D7 CSI_D2 CSI_D5 A7 A6 A13 CSI_D3 CSI_D4 CSI_D8
NC_BGA_B20 A4
A11
CSI_D6
CSI_D9
CSI_VSYNC CSI_PIXCLK CSI_HSYNC CSI_MCLK
SD1_DATA3
NC_BGA_J19
USBPHY1_UID
NC_BGA_E17 I2C1_CLK I2C1_DAT QGND
NC_BGA_H17 USBPHY1_VSSA_BIAS QGND QGND
NVCC_EMI2 QGND NVCC_EMI2 NVCC_EMI2 NVCC_EMI2 NVCC_EMI2 NVCC_EMI2 NVCC_EMI2 QVDD QGND QGND QGND NVCC_EMI1 QGND NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 NVCC_EMI1 QGND NFWE_B D3 D4 D5 G QGND NFWP_B D12 D13 D6 H
QGND
NVCC_CSI
NVCC_CSI QVDD QGND QGND QGND QVDD
12 SD0 11 QGND 10 SD7 9 SD13 8 SD15 7 A25 6 A23 5 A22 4 A19 3 A14 2 A10
NVCC_EMI1
Table 99 shows the i.MX25 ball map.
NVCC_EMI1 QGND
i.MX25 Ball Map
FEC_TDATA1 D7 D15 D14
i.MX25 Applications Processor for Automotive Products, Rev. 1
Table 99. i.MX25 Ball Map
J
4.4
Freescale Semiconductor
127
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20 SD1_CMD 19 USBPHY1_VDDA_BIAS USBPHY1_VSSA SD1_DATA2 18 USBPHY1_DM 17 USBPHY1_VBUS 16 USBPHY1_VDDA 15 QGND QGND QGND QGND QGND QGND QGND QGND NVCC_NFC NVCC_NFC NVCC_NFC QGND FEC_TX_CLK FEC_TDATA0 FEC_MDIO FEC_MDC K L QGND QGND QVDD QVDD QVDD FEC_RDATA1 FEC_RX_DV FEC_TX_EN FEC_RDATA0 M QGND QGND QGND QGND QGND QGND TAMPER_B TAMPER_A QGND QVDD NVCC_MISC NVCC_MISC NVCC_MISC KPP_ROW0 KPP_COL1 KPP_COL2 KPP_COL3 N QGND NVCC_CRM QGND QGND UPLL_VDD UPLL_GND QGND USBPHY1_DP NC_BGA_M18 GPIO_B GPIO_E GPIO_A GPIO_D
SD1_DATA0
SD1_CLK
SD1_DATA1
NC_BGA_P20 EXT_ARMCLK VSTBY_ACK GPIO_F VSTBY_REQ NVCC_SDIO QGND QGND QGND QGND MESH_D MESH_C BAT_VDD QVDD QVDD QGND QGND QGND QGND QGND QGND QGND QGND NVCC_LCDC NVCC_LCDC NVCC_LCDC NVCC_LCDC QGND UART2_RXD KPP_ROW2 KPP_ROW3 KPP_COL0 P QGND CSPI1_SS0 UART2_RTS UART2_CTS KPP_ROW1 R
POWER_FAIL
RESET_B
USBPHY1_RREF USBPHY1_UPLLVDD USBPHY1_UPLLVSS GPIO_C QGND
FUSE_VDD
QGND
Table 99. i.MX25 Ball Map (continued)
14 QGND 13 QGND 12 QVDD 11 QGND 10 QGND 9 QGND 8 QGND 7 QVDD 6 QVDD 5 QGND 4 QGND 3 QGND 2 QGND 1 QGND
QGND
QGND
QGND
QGND
QGND
QGND
QGND
QGND
QGND
QGND
CSPI1_MOSI
UART1_RTS
UART1_CTS
UART2_TXD
T
i.MX25 Applications Processor for Automotive Products, Rev. 1
QGND
128
Freescale Semiconductor
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Table 99. i.MX25 Ball Map (continued)
10 NVCC_JTAG 11 INAUX0 12 INAUX2 13 XN 14 WIPER 15 NC_BGA_U15 NC_BGA_V15 16 NC_BGA_U16 NC_BGA_V16 17 MPLL_GND 18 MPLL_VDD 19 POR_B 20 UPLL_BYPCLK CLKO
5
Revision History
Table 100. Revision History
Rev. 1 Date 10/2009 * * * * * * * * * * Revision Updated Table 1, "Ordering Information," to include new part numbers. Updated DRYICE description in Table 2, "i.MX25 Digital and Analog Modules." Updated REF signal description in Table 3, "Signal Considerations." Updated ESD damage immunity values in Table 4, "DC Absolute Maximum Ratings." Updated values in Table 10, "i.MX25 Power Mode Current Consumption." Added a note on timing in Section 3.2.1, "Power-Up Sequence." Added Table 11, "iMX25 Reduced Power Mode Current Consumption." Updated Table 51, "NFC Timing Parameters." Updated values in Table 52, "WEIM Bus Timing Parameters. Updated Table 81, "Touchscreen ADC Electrical Specifications."
Table 100 summarizes revisions to this document.
0
6/2009 Initial release.
i.MX25 Applications Processor for Automotive Products, Rev. 1 Freescale Semiconductor 129
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1 UART1_TXD CSPI1_RDY CSPI1_MISO QGND
2 UART1_RXD
3 CSPI1_SCLK
4 CONTRAST
5 LSCLK
6 VSYNC
7 HSYNC
8 LD3
9 SJC_MOD
U V W Y
CSPI1_SS1 PWM NC_BGA_Y2
OE_ACD LD15 LD11
LD14 LD13 LD10
LD12 LD9 LD7
LD8 LD6 LD4
LD5 LD2 LD0
LD1 DE_B TDO
TRSTB TDI TMS
TCK RTCK OSC32K_XTAL
REF NVCC_DRYICE OSC32K_EXTAL
INAUX1 YN OSC_BYP
YP NVCC_ADC NGND_ADC
XP NC_BGA_W14 NC_BGA_Y14
NC_BGA_V17
TEST_MODE
BOOT_MODE0 CLK_SEL
OSC24M_GND OSC24M_EXTAL
OSC24M_VDD OSC24M_XTAL
USBPHY2_VSS NC_BGA_Y17
USBPHY2_VDD USBPHY2_DP
BOOT_MODE1 QGND
USBPHY2_DM
130
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Document Number: IMX25AEC Rev. 1 10/2009
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